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Daan Vanoverloop 11 months ago
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Computergrafiek Project/graphics_project_21-22-Danacus

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Subproject commit bcf2b41b30670db5c7c4d49819346386bc4baa0d
Subproject commit 4be5abadf349c6f7293f9c990ccc941c4b897cc9

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Digitale elektronica en processoren/practicum/fourBitAdder/HA.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:54:42 04/04/2022
// Design Name:
// Module Name: HA
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HA(
input a,
input b,
output c,
output s
);
assign s = a ^ b;
assign c = a & b;
endmodule

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Digitale elektronica en processoren/practicum/fourBitAdder/HA_summary.html
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>HA Project Status (04/04/2022 - 15:13:28)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>fourBitAdder.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>HA</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Placed and Routed</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc3s200-4ft256</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Mon Apr 4 14:55:04 2022</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 04/04/2022 - 15:13:28</center>
</BODY></HTML>

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Digitale elektronica en processoren/practicum/fourBitAdder/_ngo/netlist.lst
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/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/topFour.ngc 1649077999
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Digitale elektronica en processoren/practicum/fourBitAdder/_xmsgs/map.xmsgs
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.
</msg>
<msg type="info" file="LIT" num="244" delta="new" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
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Digitale elektronica en processoren/practicum/fourBitAdder/_xmsgs/ngdbuild.xmsgs
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

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Digitale elektronica en processoren/practicum/fourBitAdder/_xmsgs/par.xmsgs
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Par" num="282" delta="new" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
</msg>
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Digitale elektronica en processoren/practicum/fourBitAdder/_xmsgs/pn_parser.xmsgs
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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Digitale elektronica en processoren/practicum/fourBitAdder/_xmsgs/trce.xmsgs
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="2698" delta="new" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="3412" delta="new" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
<msg type="info" file="Timing" num="3390" delta="new" >This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</msg>
<msg type="info" file="Timing" num="3389" delta="new" >This architecture does not support &apos;Discrete Jitter&apos; and &apos;Phase Error&apos; calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</msg>
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Digitale elektronica en processoren/practicum/fourBitAdder/_xmsgs/xst.xmsgs
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changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

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Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.gise
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Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.jhd
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MODULE fourBitAdder
SUBMODULE oneBitAdder
INSTANCE XLXI_1
SUBMODULE oneBitAdder
INSTANCE XLXI_2
SUBMODULE oneBitAdder
INSTANCE XLXI_3
SUBMODULE oneBitAdder
INSTANCE XLXI_4

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Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.sch
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<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
<attr value="spartan3" name="DeviceFamilyName">
<trait delete="all:0" />
<trait editname="all:0" />
<trait edittrait="all:0" />
</attr>
<netlist>
<signal name="A(3:0)" />
<signal name="B(3:0)" />
<signal name="Cin" />
<signal name="Cout" />
<signal name="Sum(3:0)" />
<signal name="A(0)" />
<signal name="B(0)" />
<signal name="B(2)" />
<signal name="A(2)" />
<signal name="B(1)" />
<signal name="B(3)" />
<signal name="A(3)" />
<signal name="A(1)" />
<signal name="XLXN_26" />
<signal name="XLXN_27" />
<signal name="XLXN_28" />
<signal name="Sum(2)" />
<signal name="Sum(1)" />
<signal name="Sum(0)" />
<signal name="Sum(3)" />
<port polarity="Input" name="A(3:0)" />
<port polarity="Input" name="B(3:0)" />
<port polarity="Input" name="Cin" />
<port polarity="Output" name="Cout" />
<port polarity="Output" name="Sum(3:0)" />
<blockdef name="oneBitAdder">
<timestamp>2022-4-4T12:4:40</timestamp>
<rect width="256" x="64" y="-192" height="192" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<line x2="384" y1="-32" y2="-32" x1="320" />
</blockdef>
<block symbolname="oneBitAdder" name="XLXI_4">
<blockpin signalname="A(3)" name="A" />
<blockpin signalname="B(3)" name="B" />
<blockpin signalname="XLXN_28" name="Cin" />
<blockpin signalname="Sum(3)" name="Sum" />
<blockpin signalname="Cout" name="Cout" />
</block>
<block symbolname="oneBitAdder" name="XLXI_1">
<blockpin signalname="A(0)" name="A" />
<blockpin signalname="B(0)" name="B" />
<blockpin signalname="Cin" name="Cin" />
<blockpin signalname="Sum(0)" name="Sum" />
<blockpin signalname="XLXN_26" name="Cout" />
</block>
<block symbolname="oneBitAdder" name="XLXI_2">
<blockpin signalname="A(1)" name="A" />
<blockpin signalname="B(1)" name="B" />
<blockpin signalname="XLXN_26" name="Cin" />
<blockpin signalname="Sum(1)" name="Sum" />
<blockpin signalname="XLXN_27" name="Cout" />
</block>
<block symbolname="oneBitAdder" name="XLXI_3">
<blockpin signalname="A(2)" name="A" />
<blockpin signalname="B(2)" name="B" />
<blockpin signalname="XLXN_27" name="Cin" />
<blockpin signalname="Sum(2)" name="Sum" />
<blockpin signalname="XLXN_28" name="Cout" />
</block>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
<branch name="Cout">
<wire x2="3056" y1="592" y2="592" x1="2832" />
<wire x2="3216" y1="464" y2="464" x1="3056" />
<wire x2="3056" y1="464" y2="592" x1="3056" />
</branch>
<branch name="Sum(3:0)">
<wire x2="2928" y1="304" y2="368" x1="2928" />
<wire x2="2928" y1="368" y2="720" x1="2928" />
<wire x2="2928" y1="720" y2="784" x1="2928" />
<wire x2="2928" y1="784" y2="928" x1="2928" />
<wire x2="2928" y1="928" y2="1168" x1="2928" />
<wire x2="2928" y1="1168" y2="1392" x1="2928" />
<wire x2="3216" y1="784" y2="784" x1="2928" />
</branch>
<iomarker fontsize="28" x="3216" y="464" name="Cout" orien="R0" />
<iomarker fontsize="28" x="3216" y="784" name="Sum(3:0)" orien="R0" />
<instance x="2448" y="624" name="XLXI_4" orien="R0">
</instance>
<instance x="1968" y="880" name="XLXI_3" orien="R0">
</instance>
<instance x="1440" y="1088" name="XLXI_2" orien="R0">
</instance>
<iomarker fontsize="28" x="336" y="1200" name="Cin" orien="R180" />
<branch name="Cin">
<wire x2="880" y1="1200" y2="1200" x1="336" />
</branch>
<bustap x2="656" y1="1072" y2="1072" x1="560" />
<bustap x2="592" y1="1136" y2="1136" x1="496" />
<branch name="B(0)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="688" y="1136" type="branch" />
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<wire x2="880" y1="1136" y2="1136" x1="688" />
</branch>
<branch name="B(2)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="688" y="784" type="branch" />
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<wire x2="1968" y1="784" y2="784" x1="688" />
</branch>
<branch name="A(2)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="688" y="720" type="branch" />
<wire x2="688" y1="720" y2="720" x1="656" />
<wire x2="1968" y1="720" y2="720" x1="688" />
</branch>
<branch name="A(3:0)">
<wire x2="560" y1="352" y2="352" x1="352" />
<wire x2="560" y1="352" y2="464" x1="560" />
<wire x2="560" y1="464" y2="720" x1="560" />
<wire x2="560" y1="720" y2="928" x1="560" />
<wire x2="560" y1="928" y2="1072" x1="560" />
</branch>
<branch name="A(1)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="688" y="928" type="branch" />
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</branch>
<branch name="B(1)">
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<wire x2="1440" y1="992" y2="992" x1="688" />
</branch>
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<iomarker fontsize="28" x="352" y="432" name="B(3:0)" orien="R180" />
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<branch name="B(3:0)">
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</branch>
<bustap x2="592" y1="528" y2="528" x1="496" />
<branch name="B(3)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="688" y="528" type="branch" />
<wire x2="688" y1="528" y2="528" x1="592" />
<wire x2="2448" y1="528" y2="528" x1="688" />
</branch>
<bustap x2="656" y1="464" y2="464" x1="560" />
<branch name="A(3)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="688" y="464" type="branch" />
<wire x2="688" y1="464" y2="464" x1="656" />
<wire x2="2448" y1="464" y2="464" x1="688" />
</branch>
<branch name="A(0)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="688" y="1072" type="branch" />
<wire x2="688" y1="1072" y2="1072" x1="656" />
<wire x2="880" y1="1072" y2="1072" x1="688" />
</branch>
<instance x="880" y="1232" name="XLXI_1" orien="R0">
</instance>
<branch name="XLXN_26">
<wire x2="1344" y1="1200" y2="1200" x1="1264" />
<wire x2="1344" y1="1056" y2="1200" x1="1344" />
<wire x2="1440" y1="1056" y2="1056" x1="1344" />
</branch>
<branch name="XLXN_27">
<wire x2="1888" y1="1056" y2="1056" x1="1824" />
<wire x2="1888" y1="848" y2="1056" x1="1888" />
<wire x2="1968" y1="848" y2="848" x1="1888" />
</branch>
<branch name="XLXN_28">
<wire x2="2400" y1="848" y2="848" x1="2352" />
<wire x2="2400" y1="592" y2="848" x1="2400" />
<wire x2="2448" y1="592" y2="592" x1="2400" />
</branch>
<bustap x2="2832" y1="720" y2="720" x1="2928" />
<branch name="Sum(2)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2752" y="720" type="branch" />
<wire x2="2752" y1="720" y2="720" x1="2352" />
<wire x2="2832" y1="720" y2="720" x1="2752" />
</branch>
<bustap x2="2832" y1="928" y2="928" x1="2928" />
<branch name="Sum(1)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2752" y="928" type="branch" />
<wire x2="2752" y1="928" y2="928" x1="1824" />
<wire x2="2832" y1="928" y2="928" x1="2752" />
</branch>
<bustap x2="2832" y1="1168" y2="1168" x1="2928" />
<branch name="Sum(0)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2768" y="1168" type="branch" />
<wire x2="1328" y1="1072" y2="1072" x1="1264" />
<wire x2="1328" y1="1072" y2="1168" x1="1328" />
<wire x2="2768" y1="1168" y2="1168" x1="1328" />
<wire x2="2832" y1="1168" y2="1168" x1="2768" />
</branch>
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<branch name="Sum(3)">
<attrtext style="alignment:SOFT-TVCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2832" y="432" type="branch" />
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<wire x2="2832" y1="432" y2="464" x1="2832" />
</branch>
</sheet>
</drawing>

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Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.sym
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="fourBitAdder">
<symboltype>BLOCK</symboltype>
<timestamp>2022-4-4T12:42:13</timestamp>
<pin polarity="Input" x="0" y="-160" name="A(3:0)" />
<pin polarity="Input" x="0" y="-96" name="B(3:0)" />
<pin polarity="Input" x="0" y="-32" name="Cin" />
<pin polarity="Output" x="384" y="-160" name="Cout" />
<pin polarity="Output" x="384" y="-96" name="Sum(3:0)" />
<graph>
<rect width="256" x="64" y="-192" height="192" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-200" type="symbol" />
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<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin A(3:0)" />
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<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin B(3:0)" />
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<line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin Cin" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin Cout" />
<line x2="384" y1="-96" y2="-96" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin Sum(3:0)" />
<rect width="64" x="320" y="-108" height="24" />
</graph>
</symbol>

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Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.vhf
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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : sch2hdl
-- / / Filename : fourBitAdder.vhf
-- /___/ /\ Timestamp : 04/04/2022 14:53:35
-- \ \ / \
-- \___\/\___\
--
--Command: sch2hdl -intstyle ise -family spartan3 -flat -suppress -vhdl "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.vhf" -w "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.sch"
--Design Name: fourBitAdder
--Device: spartan3
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesized and simulated, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity fourBitAdder is
port ( A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
Cin : in std_logic;
Cout : out std_logic;
Sum : out std_logic_vector (3 downto 0));
end fourBitAdder;
architecture BEHAVIORAL of fourBitAdder is
signal XLXN_26 : std_logic;
signal XLXN_27 : std_logic;
signal XLXN_28 : std_logic;
component oneBitAdder
port ( A : in std_logic;
B : in std_logic;
Cin : in std_logic;
Sum : out std_logic;
Cout : out std_logic);
end component;
begin
XLXI_1 : oneBitAdder
port map (A=>A(0),
B=>B(0),
Cin=>Cin,
Cout=>XLXN_26,
Sum=>Sum(0));
XLXI_2 : oneBitAdder
port map (A=>A(1),
B=>B(1),
Cin=>XLXN_26,
Cout=>XLXN_27,
Sum=>Sum(1));
XLXI_3 : oneBitAdder
port map (A=>A(2),
B=>B(2),
Cin=>XLXN_27,
Cout=>XLXN_28,
Sum=>Sum(2));
XLXI_4 : oneBitAdder
port map (A=>A(3),
B=>B(3),
Cin=>XLXN_28,
Cout=>Cout,
Sum=>Sum(3));
end BEHAVIORAL;

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Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.xise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="HA.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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<!-- -->
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Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder_fourBitAdder_sch_tb_beh.prj
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verilog work "HA.v"
verilog work "oneBitAdder.v"
vhdl work "fourBitAdder.vhf"
verilog work "fourBitTest.v"
verilog work "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"

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Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder_fourBitAdder_sch_tb_isim_beh.exe
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Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder_fourBitAdder_sch_tb_isim_beh.wdb
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Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder_fourBitAdder_sch_tb_stx_beh.prj
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verilog isim_temp "HA.v"
verilog isim_temp "oneBitAdder.v"
verilog isim_temp "fourBitTest.v"
verilog isim_temp "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"

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Digitale elektronica en processoren/practicum/fourBitAdder/fourBitTest.v
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// Verilog test fixture created from schematic /home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.sch - Mon Apr 4 14:43:23 2022
`timescale 1ns / 1ps
module fourBitAdder_fourBitAdder_sch_tb();
// Inputs
reg [3:0] A;
reg [3:0] B;
reg Cin;
// Output
wire Cout;
wire [3:0] Sum;
// Bidirs
// Instantiate the UUT
fourBitAdder UUT (
.A(A),
.B(B),
.Cin(Cin),
.Cout(Cout),
.Sum(Sum)
);
initial begin
// All inputs 0, Cout and Sum should be 0
A = 0;
B = 0;
Cin = 0;
#20;
// A and B bits 1
A = 4'b1111;
B = 4'b1111;
Cin = 0;
#20;
A = 4'b1111;
B = 4'b1111;
Cin = 1;
#20;
A = 4'b0001;
B = 4'b1001;
Cin = 1;
// Expected: Sum = b1011;
end
endmodule

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Digitale elektronica en processoren/practicum/fourBitAdder/fuse.log
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Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o /home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder_fourBitAdder_sch_tb_isim_beh.exe -prj /home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder_fourBitAdder_sch_tb_beh.prj work.fourBitAdder_fourBitAdder_sch_tb work.glbl
ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 12
Turning on mult-threading, number of parallel sub-compilation jobs: 24
Determining compilation order of HDL files
Analyzing Verilog file "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/HA.v" into library work
Analyzing Verilog file "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/oneBitAdder.v" into library work
Analyzing Verilog file "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitTest.v" into library work
Analyzing Verilog file "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work
Parsing VHDL file "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.vhf" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 100740 KB
Fuse CPU Usage: 480 ms
Compiling module HA
Compiling module oneBitAdder
Compiling module fourBitAdder_fourBitAdder_sch_tb
Compiling module glbl
Compiling package standard
Compiling package std_logic_1164
Compiling package numeric_std
Compiling package vcomponents
Compiling package vl_types
Compiling architecture behavioral of entity fourBitAdder [fourbitadder_default]
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 7 VHDL Units
Compiled 4 Verilog Units
Built simulation executable /home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder_fourBitAdder_sch_tb_isim_beh.exe
Fuse Memory Usage: 1726436 KB
Fuse CPU Usage: 530 ms
GCC CPU Usage: 1220 ms

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Digitale elektronica en processoren/practicum/fourBitAdder/fuse.xmsgs
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

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Digitale elektronica en processoren/practicum/fourBitAdder/fuseRelaunch.cmd
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-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -o "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder_fourBitAdder_sch_tb_isim_beh.exe" -prj "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder_fourBitAdder_sch_tb_beh.prj" "work.fourBitAdder_fourBitAdder_sch_tb" "work.glbl"

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Digitale elektronica en processoren/practicum/fourBitAdder/ioConnections.sch
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Digitale elektronica en processoren/practicum/fourBitAdder/iseconfig/HA.xreport
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<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2022-04-04T15:13:07</DateModified>
<ModuleName>topFour</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/iseconfig/HA.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder</ImplementationReportsDirectory>
<DateInitialized>2022-04-04T15:13:07</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="topFour_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="topFour_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="topFour_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="topFour_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="topFour_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="topFour.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="topFour_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="topFour_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="topFour.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="topFour_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="topFour_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
</viewgroup>
<viewgroup label="XPS Reports" >
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="topFour.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="topFour.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="topFour.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="topFour.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="topFour.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="topFour_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="topFour.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Clock Report" target="Generating Clock Report" />
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
</view>
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="topFour.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="topFour.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="topFour.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="topFour.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="topFour.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
</view>
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/topFour_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/topFour_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="topFour_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="topFour_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="topFour_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/topFour_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="topFour_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="topFour_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="topFour.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="topFour_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="topFour.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="topFour.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="topFour.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="topFour.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="topFour_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/topFour_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="topFour_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>