master
Daan Vanoverloop 2 months ago
parent db403d3f74
commit 182effcf4c
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Subproject commit bcf2b41b30670db5c7c4d49819346386bc4baa0d
Subproject commit 4be5abadf349c6f7293f9c990ccc941c4b897cc9

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:54:42 04/04/2022
// Design Name:
// Module Name: HA
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HA(
input a,
input b,
output c,
output s
);
assign s = a ^ b;
assign c = a & b;
endmodule

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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>HA Project Status (04/04/2022 - 15:13:28)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>fourBitAdder.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>HA</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Placed and Routed</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc3s200-4ft256</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Mon Apr 4 14:55:04 2022</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 04/04/2022 - 15:13:28</center>
</BODY></HTML>

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/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/topFour.ngc 1649077999
OK

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.
</msg>
<msg type="info" file="LIT" num="244" delta="new" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>
</messages>

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Par" num="282" delta="new" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
</msg>
</messages>

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
</messages>

@ -0,0 +1,21 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="2698" delta="new" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="3412" delta="new" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
<msg type="info" file="Timing" num="3390" delta="new" >This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</msg>
<msg type="info" file="Timing" num="3389" delta="new" >This architecture does not support &apos;Discrete Jitter&apos; and &apos;Phase Error&apos; calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</msg>
</messages>

@ -0,0 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

@ -0,0 +1,248 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<!-- For tool use only. Do not edit. -->
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<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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@ -0,0 +1,9 @@
MODULE fourBitAdder
SUBMODULE oneBitAdder
INSTANCE XLXI_1
SUBMODULE oneBitAdder
INSTANCE XLXI_2
SUBMODULE oneBitAdder
INSTANCE XLXI_3
SUBMODULE oneBitAdder
INSTANCE XLXI_4

@ -0,0 +1,207 @@
<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
<attr value="spartan3" name="DeviceFamilyName">
<trait delete="all:0" />
<trait editname="all:0" />
<trait edittrait="all:0" />
</attr>
<netlist>
<signal name="A(3:0)" />
<signal name="B(3:0)" />
<signal name="Cin" />
<signal name="Cout" />
<signal name="Sum(3:0)" />
<signal name="A(0)" />
<signal name="B(0)" />
<signal name="B(2)" />
<signal name="A(2)" />
<signal name="B(1)" />
<signal name="B(3)" />
<signal name="A(3)" />
<signal name="A(1)" />
<signal name="XLXN_26" />
<signal name="XLXN_27" />
<signal name="XLXN_28" />
<signal name="Sum(2)" />
<signal name="Sum(1)" />
<signal name="Sum(0)" />
<signal name="Sum(3)" />
<port polarity="Input" name="A(3:0)" />
<port polarity="Input" name="B(3:0)" />
<port polarity="Input" name="Cin" />
<port polarity="Output" name="Cout" />
<port polarity="Output" name="Sum(3:0)" />
<blockdef name="oneBitAdder">
<timestamp>2022-4-4T12:4:40</timestamp>
<rect width="256" x="64" y="-192" height="192" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<line x2="384" y1="-32" y2="-32" x1="320" />
</blockdef>
<block symbolname="oneBitAdder" name="XLXI_4">
<blockpin signalname="A(3)" name="A" />
<blockpin signalname="B(3)" name="B" />
<blockpin signalname="XLXN_28" name="Cin" />
<blockpin signalname="Sum(3)" name="Sum" />
<blockpin signalname="Cout" name="Cout" />
</block>
<block symbolname="oneBitAdder" name="XLXI_1">
<blockpin signalname="A(0)" name="A" />
<blockpin signalname="B(0)" name="B" />
<blockpin signalname="Cin" name="Cin" />
<blockpin signalname="Sum(0)" name="Sum" />
<blockpin signalname="XLXN_26" name="Cout" />
</block>
<block symbolname="oneBitAdder" name="XLXI_2">
<blockpin signalname="A(1)" name="A" />
<blockpin signalname="B(1)" name="B" />
<blockpin signalname="XLXN_26" name="Cin" />
<blockpin signalname="Sum(1)" name="Sum" />
<blockpin signalname="XLXN_27" name="Cout" />
</block>
<block symbolname="oneBitAdder" name="XLXI_3">
<blockpin signalname="A(2)" name="A" />
<blockpin signalname="B(2)" name="B" />
<blockpin signalname="XLXN_27" name="Cin" />
<blockpin signalname="Sum(2)" name="Sum" />
<blockpin signalname="XLXN_28" name="Cout" />
</block>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
<branch name="Cout">
<wire x2="3056" y1="592" y2="592" x1="2832" />
<wire x2="3216" y1="464" y2="464" x1="3056" />
<wire x2="3056" y1="464" y2="592" x1="3056" />
</branch>
<branch name="Sum(3:0)">
<wire x2="2928" y1="304" y2="368" x1="2928" />
<wire x2="2928" y1="368" y2="720" x1="2928" />
<wire x2="2928" y1="720" y2="784" x1="2928" />
<wire x2="2928" y1="784" y2="928" x1="2928" />
<wire x2="2928" y1="928" y2="1168" x1="2928" />
<wire x2="2928" y1="1168" y2="1392" x1="2928" />
<wire x2="3216" y1="784" y2="784" x1="2928" />
</branch>
<iomarker fontsize="28" x="3216" y="464" name="Cout" orien="R0" />
<iomarker fontsize="28" x="3216" y="784" name="Sum(3:0)" orien="R0" />
<instance x="2448" y="624" name="XLXI_4" orien="R0">
</instance>
<instance x="1968" y="880" name="XLXI_3" orien="R0">
</instance>
<instance x="1440" y="1088" name="XLXI_2" orien="R0">
</instance>
<iomarker fontsize="28" x="336" y="1200" name="Cin" orien="R180" />
<branch name="Cin">
<wire x2="880" y1="1200" y2="1200" x1="336" />
</branch>
<bustap x2="656" y1="1072" y2="1072" x1="560" />
<bustap x2="592" y1="1136" y2="1136" x1="496" />
<branch name="B(0)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="688" y="1136" type="branch" />
<wire x2="688" y1="1136" y2="1136" x1="592" />
<wire x2="880" y1="1136" y2="1136" x1="688" />
</branch>
<branch name="B(2)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="688" y="784" type="branch" />
<wire x2="688" y1="784" y2="784" x1="592" />
<wire x2="1968" y1="784" y2="784" x1="688" />
</branch>
<branch name="A(2)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="688" y="720" type="branch" />
<wire x2="688" y1="720" y2="720" x1="656" />
<wire x2="1968" y1="720" y2="720" x1="688" />
</branch>
<branch name="A(3:0)">
<wire x2="560" y1="352" y2="352" x1="352" />
<wire x2="560" y1="352" y2="464" x1="560" />
<wire x2="560" y1="464" y2="720" x1="560" />
<wire x2="560" y1="720" y2="928" x1="560" />
<wire x2="560" y1="928" y2="1072" x1="560" />
</branch>
<branch name="A(1)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="688" y="928" type="branch" />
<wire x2="688" y1="928" y2="928" x1="656" />
<wire x2="1440" y1="928" y2="928" x1="688" />
</branch>
<branch name="B(1)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="688" y="992" type="branch" />
<wire x2="688" y1="992" y2="992" x1="592" />
<wire x2="1440" y1="992" y2="992" x1="688" />
</branch>
<bustap x2="656" y1="720" y2="720" x1="560" />
<bustap x2="592" y1="784" y2="784" x1="496" />
<bustap x2="656" y1="928" y2="928" x1="560" />
<bustap x2="592" y1="992" y2="992" x1="496" />
<iomarker fontsize="28" x="352" y="432" name="B(3:0)" orien="R180" />
<iomarker fontsize="28" x="352" y="352" name="A(3:0)" orien="R180" />
<branch name="B(3:0)">
<wire x2="496" y1="432" y2="432" x1="352" />
<wire x2="496" y1="432" y2="528" x1="496" />
<wire x2="496" y1="528" y2="784" x1="496" />
<wire x2="496" y1="784" y2="992" x1="496" />
<wire x2="496" y1="992" y2="1136" x1="496" />
</branch>
<bustap x2="592" y1="528" y2="528" x1="496" />
<branch name="B(3)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="688" y="528" type="branch" />
<wire x2="688" y1="528" y2="528" x1="592" />
<wire x2="2448" y1="528" y2="528" x1="688" />
</branch>
<bustap x2="656" y1="464" y2="464" x1="560" />
<branch name="A(3)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="688" y="464" type="branch" />
<wire x2="688" y1="464" y2="464" x1="656" />
<wire x2="2448" y1="464" y2="464" x1="688" />
</branch>
<branch name="A(0)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="688" y="1072" type="branch" />
<wire x2="688" y1="1072" y2="1072" x1="656" />
<wire x2="880" y1="1072" y2="1072" x1="688" />
</branch>
<instance x="880" y="1232" name="XLXI_1" orien="R0">
</instance>
<branch name="XLXN_26">
<wire x2="1344" y1="1200" y2="1200" x1="1264" />
<wire x2="1344" y1="1056" y2="1200" x1="1344" />
<wire x2="1440" y1="1056" y2="1056" x1="1344" />
</branch>
<branch name="XLXN_27">
<wire x2="1888" y1="1056" y2="1056" x1="1824" />
<wire x2="1888" y1="848" y2="1056" x1="1888" />
<wire x2="1968" y1="848" y2="848" x1="1888" />
</branch>
<branch name="XLXN_28">
<wire x2="2400" y1="848" y2="848" x1="2352" />
<wire x2="2400" y1="592" y2="848" x1="2400" />
<wire x2="2448" y1="592" y2="592" x1="2400" />
</branch>
<bustap x2="2832" y1="720" y2="720" x1="2928" />
<branch name="Sum(2)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2752" y="720" type="branch" />
<wire x2="2752" y1="720" y2="720" x1="2352" />
<wire x2="2832" y1="720" y2="720" x1="2752" />
</branch>
<bustap x2="2832" y1="928" y2="928" x1="2928" />
<branch name="Sum(1)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2752" y="928" type="branch" />
<wire x2="2752" y1="928" y2="928" x1="1824" />
<wire x2="2832" y1="928" y2="928" x1="2752" />
</branch>
<bustap x2="2832" y1="1168" y2="1168" x1="2928" />
<branch name="Sum(0)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2768" y="1168" type="branch" />
<wire x2="1328" y1="1072" y2="1072" x1="1264" />
<wire x2="1328" y1="1072" y2="1168" x1="1328" />
<wire x2="2768" y1="1168" y2="1168" x1="1328" />
<wire x2="2832" y1="1168" y2="1168" x1="2768" />
</branch>
<bustap x2="2832" y1="368" y2="368" x1="2928" />
<branch name="Sum(3)">
<attrtext style="alignment:SOFT-TVCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2832" y="432" type="branch" />
<wire x2="2832" y1="368" y2="432" x1="2832" />
<wire x2="2832" y1="432" y2="464" x1="2832" />
</branch>
</sheet>
</drawing>

@ -0,0 +1,27 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="fourBitAdder">
<symboltype>BLOCK</symboltype>
<timestamp>2022-4-4T12:42:13</timestamp>
<pin polarity="Input" x="0" y="-160" name="A(3:0)" />
<pin polarity="Input" x="0" y="-96" name="B(3:0)" />
<pin polarity="Input" x="0" y="-32" name="Cin" />
<pin polarity="Output" x="384" y="-160" name="Cout" />
<pin polarity="Output" x="384" y="-96" name="Sum(3:0)" />
<graph>
<rect width="256" x="64" y="-192" height="192" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-200" type="symbol" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin A(3:0)" />
<rect width="64" x="0" y="-172" height="24" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin B(3:0)" />
<rect width="64" x="0" y="-108" height="24" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin Cin" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin Cout" />
<line x2="384" y1="-96" y2="-96" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin Sum(3:0)" />
<rect width="64" x="320" y="-108" height="24" />
</graph>
</symbol>

@ -0,0 +1,79 @@
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : sch2hdl
-- / / Filename : fourBitAdder.vhf
-- /___/ /\ Timestamp : 04/04/2022 14:53:35
-- \ \ / \
-- \___\/\___\
--
--Command: sch2hdl -intstyle ise -family spartan3 -flat -suppress -vhdl "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.vhf" -w "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.sch"
--Design Name: fourBitAdder
--Device: spartan3
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesized and simulated, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity fourBitAdder is
port ( A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
Cin : in std_logic;
Cout : out std_logic;
Sum : out std_logic_vector (3 downto 0));
end fourBitAdder;
architecture BEHAVIORAL of fourBitAdder is
signal XLXN_26 : std_logic;
signal XLXN_27 : std_logic;
signal XLXN_28 : std_logic;
component oneBitAdder
port ( A : in std_logic;
B : in std_logic;
Cin : in std_logic;
Sum : out std_logic;
Cout : out std_logic);
end component;
begin
XLXI_1 : oneBitAdder
port map (A=>A(0),
B=>B(0),
Cin=>Cin,
Cout=>XLXN_26,
Sum=>Sum(0));
XLXI_2 : oneBitAdder
port map (A=>A(1),
B=>B(1),
Cin=>XLXN_26,
Cout=>XLXN_27,
Sum=>Sum(1));
XLXI_3 : oneBitAdder
port map (A=>A(2),
B=>B(2),
Cin=>XLXN_27,
Cout=>XLXN_28,
Sum=>Sum(2));
XLXI_4 : oneBitAdder
port map (A=>A(3),
B=>B(3),
Cin=>XLXN_28,
Cout=>Cout,
Sum=>Sum(3));
end BEHAVIORAL;

@ -0,0 +1,411 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="HA.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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<file xil_pn:name="oneBitAdder.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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<file xil_pn:name="oneBitTest.v" xil_pn:type="FILE_VERILOG">
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<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s200" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="topFour.sch" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="topFour" xil_pn:valueState="default"/>
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<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="ft256" xil_pn:valueState="default"/>
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<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="topFour_timesim.vhd" xil_pn:valueState="default"/>
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<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
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<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
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<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
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<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
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<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="Schematic" xil_pn:valueState="non-default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
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@ -0,0 +1,5 @@
verilog work "HA.v"
verilog work "oneBitAdder.v"
vhdl work "fourBitAdder.vhf"
verilog work "fourBitTest.v"
verilog work "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"

@ -0,0 +1,4 @@
verilog isim_temp "HA.v"
verilog isim_temp "oneBitAdder.v"
verilog isim_temp "fourBitTest.v"
verilog isim_temp "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"

@ -0,0 +1,57 @@
// Verilog test fixture created from schematic /home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.sch - Mon Apr 4 14:43:23 2022
`timescale 1ns / 1ps
module fourBitAdder_fourBitAdder_sch_tb();
// Inputs
reg [3:0] A;
reg [3:0] B;
reg Cin;
// Output
wire Cout;
wire [3:0] Sum;
// Bidirs
// Instantiate the UUT
fourBitAdder UUT (
.A(A),
.B(B),
.Cin(Cin),
.Cout(Cout),
.Sum(Sum)
);
initial begin
// All inputs 0, Cout and Sum should be 0
A = 0;
B = 0;
Cin = 0;
#20;
// A and B bits 1
A = 4'b1111;
B = 4'b1111;
Cin = 0;
#20;
A = 4'b1111;
B = 4'b1111;
Cin = 1;
#20;
A = 4'b0001;
B = 4'b1001;
Cin = 1;
// Expected: Sum = b1011;
end
endmodule

@ -0,0 +1,32 @@
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o /home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder_fourBitAdder_sch_tb_isim_beh.exe -prj /home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder_fourBitAdder_sch_tb_beh.prj work.fourBitAdder_fourBitAdder_sch_tb work.glbl
ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 12
Turning on mult-threading, number of parallel sub-compilation jobs: 24
Determining compilation order of HDL files
Analyzing Verilog file "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/HA.v" into library work
Analyzing Verilog file "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/oneBitAdder.v" into library work
Analyzing Verilog file "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitTest.v" into library work
Analyzing Verilog file "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work
Parsing VHDL file "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.vhf" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 100740 KB
Fuse CPU Usage: 480 ms
Compiling module HA
Compiling module oneBitAdder
Compiling module fourBitAdder_fourBitAdder_sch_tb
Compiling module glbl
Compiling package standard
Compiling package std_logic_1164
Compiling package numeric_std
Compiling package vcomponents
Compiling package vl_types
Compiling architecture behavioral of entity fourBitAdder [fourbitadder_default]
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 7 VHDL Units
Compiled 4 Verilog Units
Built simulation executable /home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder_fourBitAdder_sch_tb_isim_beh.exe
Fuse Memory Usage: 1726436 KB
Fuse CPU Usage: 530 ms
GCC CPU Usage: 1220 ms

@ -0,0 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

@ -0,0 +1 @@
-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -o "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder_fourBitAdder_sch_tb_isim_beh.exe" -prj "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder_fourBitAdder_sch_tb_beh.prj" "work.fourBitAdder_fourBitAdder_sch_tb" "work.glbl"

@ -0,0 +1,215 @@
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