master
Daan Vanoverloop 1 month ago
parent 8111d8f958
commit dce7c0122e
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- trade off beter uitleggen: grootte lichtbron, pixel footprint
- geen functienamen uit code gebruiken

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Subproject commit 12e8b4884e0ad2f4745b5898e8d508e0dd4c750d

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build:
pandoc -t pdf -o verslag.pdf verslag.md

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---
title: 'Digitale electronica en processoren: practicum 1'
geometry: margin=2cm
author:
- Daan Vanoverloop
---
# Verilog beschrijving
```verilog
`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company: KU Leuven
// Module Name: verkeerslicht
// Project Name: verkeerslicht
// Revision 0.01 - File Created
// Additional notes:
// - Parameter BASE_FREQ is added to speed up simulation
// - Assumption: 2*FREQ <= BASE_FREQ <= 50000000 (default, Xilinx clock)
//////////////////////////////////////////////////////////////////////////////////
module verkeerslicht(
input clk,
input reset,
input voet,
input auto,
output reg hw_g,
output reg hw_o,
output reg hw_r,
output reg zs_g,
output reg zs_o,
output reg zs_r
);
// Parameter om simulatie te kunnen versnellen
parameter BASE_FREQ = 50_000_000; // 50 Mhz Xilinx klok
// Gereduceerde klokfrequentie (100 Hz) op 'ce' (clock enable).
// Enkel te gebuiken samen met clk!
parameter FREQ = 100;
wire ce;
prescaler #(.new_freq(FREQ), .old_freq(BASE_FREQ)) maak_ce (clk, reset, ce);
// Teller voor lichten
reg [8:0] Q;
reg herstart_teller = 1'b0;
always @(posedge clk, posedge reset) begin
if (reset)
Q <= 0;
else if (ce)
Q <= herstart_teller? 0: Q + 1;
end
// Timing lichten: parameters M_HWG, M_ZSG, M_O, M_R
// M_* = maximum tellerwaarde voor *
parameter M_HWG = 400;
parameter M_ZSG = 200;
parameter M_O = 100;
parameter M_R = 100;
// Definitie toestanden
// Kies als reset-toestand een veilige toestand (HW en ZS rood),
// waarbij daarna men zo snel mogelijk naar groen op HW gaat.
reg [2:0] CurrentState, NextState;
parameter HW_G = 3'b000;
parameter HW_O = 3'b001;
parameter HW_R = 3'b011;
parameter ZS_G = 3'b111;
parameter ZS_O = 3'b101;
parameter ZS_R = 3'b100;
initial CurrentState = ZS_R;
// Knop voetgangers
// State register
always @(posedge clk, posedge reset)
if (reset)
CurrentState <= ZS_R;
else
CurrentState <= NextState;
// Next state logic
always @(CurrentState, posedge Q, posedge ce) begin
if (ce == 1)
case (CurrentState)
HW_G: if (Q < M_HWG)
NextState = HW_G;
else
NextState = HW_O;
HW_O: if (Q < M_O)
NextState = HW_O;
else
NextState = HW_R;
HW_R: if (Q < M_R)
NextState = HW_R;
else
NextState = ZS_G;
ZS_G: if (Q < M_ZSG)
NextState = ZS_G;
else
NextState = ZS_O;
ZS_O: if (Q < M_O)
NextState = ZS_O;
else
NextState = ZS_R;
ZS_R: if (Q < M_R)
NextState = ZS_R;
else
NextState = HW_G;
default: NextState = ZS_R;
endcase
if (CurrentState != NextState)
herstart_teller = 1;
else
herstart_teller = 0;
end
// Output logic
always @(CurrentState) begin
herstart_teller = 1;
hw_g = 0;
hw_o = 0;
hw_r = 0;
zs_g = 0;
zs_o = 0;
zs_r = 0;
case (CurrentState)
HW_G: begin
hw_g = 1;
zs_r = 1;
end
HW_O: begin
hw_o = 1;
zs_r = 1;
end
HW_R: begin
hw_r = 1;
zs_r = 1;
end
ZS_G: begin
hw_r = 1;
zs_g = 1;
end
ZS_O: begin
hw_r = 1;
zs_o = 1;
end
ZS_R: begin
hw_r = 1;
zs_r = 1;
end
default: ;
endcase
end
endmodule
```
# Simulatieresultaten
In deze sectie wordt het simulatieresultaat van het verkeerslicht gegeven. Er was geen tijd om de geavanceerde aansturing te implementeren.
Als stimulus werd het reset signaal voor een korte periode op $1$ gezet.
![Overzicht van het hele simulatieresultaat](./result.png)
Hierop is duidelijk zichtbaar dat de verkeerslichten nooit tegelijkertijd groen zijn en dat een verkeerslicht eerst oranje wordt voordat het rood wordt.
# Bespreking
Bij de implementatie had ik wat moeite met de code voor `herstart_teller`. Dit zou eigenlijk in de output logic moeten, maar deze hangt niet af van de huidige toestand,
maar van de overgang van een toestand naar een andere toestand. Daarom heb ik deze in de next state logic gezet, zodat deze op $1$ gezet wordt wanneer de toestand
verandert naar een andere toestand.
Voor de output logic heb ik ervoor gekozen om alle output variabelen eerst op $0$ te zetten en dan in de case statement de variabelen die op $1$ moeten staan
op $1$ zetten. Zo moet ik niet in elke branch herhalen dat alle andere variabelen op $0$ moeten staan.

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht.v&quot; into library work</arg>
</msg>
</messages>

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net "clk" loc="T9";
net "reset" loc="L14";
net "hw_g" loc="P11";
net "hw_o" loc="P12";
net "hw_r" loc="N12";
net "zs_g" loc="P13";
net "zs_o" loc="N14";
net "zs_r" loc="L12";
net "voet" loc="L13";
net "auto" loc="K13";

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Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -o "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb_isim_beh.exe" -prj "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb_beh.prj" "work.verkeerslicht_tb" "work.glbl"
ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16
Determining compilation order of HDL files
Analyzing Verilog file "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/prescaler.v" into library work
Analyzing Verilog file "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht.v" into library work
Analyzing Verilog file "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb.v" into library work
Analyzing Verilog file "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 82476 KB
Fuse CPU Usage: 1160 ms
Compiling module prescaler(new_freq=100,old_freq=...
Compiling module verkeerslicht(BASE_FREQ=1000)
Compiling module verkeerslicht_tb
Compiling module glbl
Time Resolution for simulation is 1ps.
Compiled 4 Verilog Units
Built simulation executable /var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb_isim_beh.exe
Fuse Memory Usage: 1167000 KB
Fuse CPU Usage: 1170 ms
GCC CPU Usage: 200 ms

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

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-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -o "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb_isim_beh.exe" -prj "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb_beh.prj" "work.verkeerslicht_tb" "work.glbl"

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<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="2" owner="projectmgr" name="verkeerslicht" >
<!--This is an ISE project configuration file.-->
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>verkeerslicht (/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht.v)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000131000000020000000000000000000000000200000064ffffffff000000810000000300000002000001310000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>verkeerslicht (/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht.v)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design</ClosedNode>
<ClosedNode>Synthesize - XST</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
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<CurrentItem>conn.ucf</CurrentItem>
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<ItemView guiview="Library" >
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<ClosedNodesVersion>1</ClosedNodesVersion>
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</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
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<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
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</SelectedItems>
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@ -0,0 +1,3 @@
onerror {resume}
wave add /
run 35 sec;

@ -0,0 +1,22 @@
ISim log file
Running: /var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb_isim_beh.wdb
ISim P.20131013 (signature 0xfbc00daa)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 35 sec
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim P.20131013 (signature 0xfbc00daa)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 35 sec
Simulator is doing circuit initialization process.
Finished circuit initialization process.
# exit 0

@ -0,0 +1,16 @@
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ISimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value></xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>1170 ms, 1167000 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>27</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>24</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>4</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>25</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>35 s</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.11 sec, 258207 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
</xtag-section>
</TABLE>

@ -0,0 +1,29 @@
Command line:
verkeerslicht_tb_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 38431
Fri Apr 29 12:58:02 2022
Elaboration Time: 0.02 sec
Current Memory Usage: 183.759 Meg
Total Signals : 27
Total Nets : 24
Total Signal Drivers : 16
Total Blocks : 4
Total Primitive Blocks : 2
Total Processes : 25
Total Traceable Variables : 50
Total Scalar Nets and Variables : 525
Total Line Count : 91
Total Simulation Time: 0.11 sec
Current Memory Usage: 259.26 Meg
Fri Apr 29 13:28:57 2022

@ -0,0 +1,365 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/prescaler.v";
static int ng1[] = {1, 0};
static int ng2[] = {0, 0};
static void Always_25_0(char *t0)
{
char t15[8];
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
unsigned int t6;
unsigned int t7;
unsigned int t8;
unsigned int t9;
unsigned int t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t16;
LAB0: t1 = (t0 + 3088U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(25, ng0);
t2 = (t0 + 3656);
*((int *)t2) = 1;
t3 = (t0 + 3120);
*((char **)t3) = t2;
*((char **)t1) = &&LAB4;
LAB1: return;
LAB4: xsi_set_current_line(26, ng0);
t4 = (t0 + 1616U);
t5 = *((char **)t4);
t4 = (t5 + 4);
t6 = *((unsigned int *)t4);
t7 = (~(t6));
t8 = *((unsigned int *)t5);
t9 = (t8 & t7);
t10 = (t9 != 0);
if (t10 > 0)
goto LAB5;
LAB6: xsi_set_current_line(28, ng0);
t2 = (t0 + 2176);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 4);
t6 = *((unsigned int *)t5);
t7 = (~(t6));
t8 = *((unsigned int *)t4);
t9 = (t8 & t7);
t10 = (t9 != 0);
if (t10 > 0)
goto LAB8;
LAB9: xsi_set_current_line(31, ng0);
t2 = (t0 + 744);
t3 = *((char **)t2);
t2 = (t0 + 2176);
xsi_vlogvar_wait_assign_value(t2, t3, 0, 0, 25, 0LL);
LAB10:
LAB7: goto LAB2;
LAB5: xsi_set_current_line(27, ng0);
t11 = (t0 + 744);
t12 = *((char **)t11);
t11 = (t0 + 2176);
xsi_vlogvar_wait_assign_value(t11, t12, 0, 0, 25, 0LL);
goto LAB7;
LAB8: xsi_set_current_line(29, ng0);
t11 = (t0 + 2176);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = ((char*)((ng1)));
memset(t15, 0, 8);
xsi_vlog_unsigned_minus(t15, 32, t13, 25, t14, 32);
t16 = (t0 + 2176);
xsi_vlogvar_wait_assign_value(t16, t15, 0, 0, 25, 0LL);
goto LAB10;
}
static void Cont_33_1(char *t0)
{
char t6[8];
char t22[8];
char t41[8];
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t7;
char *t8;
unsigned int t9;
unsigned int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
unsigned int t14;
unsigned int t15;
unsigned int t16;
unsigned int t17;
unsigned int t18;
unsigned int t19;
unsigned int t20;
char *t21;
char *t23;
char *t24;
unsigned int t25;
unsigned int t26;
unsigned int t27;
unsigned int t28;
unsigned int t29;
char *t30;
char *t31;
char *t32;
unsigned int t33;
unsigned int t34;
unsigned int t35;
unsigned int t36;
unsigned int t37;
unsigned int t38;
unsigned int t39;
unsigned int t40;
unsigned int t42;
unsigned int t43;
unsigned int t44;
char *t45;
char *t46;
char *t47;
unsigned int t48;
unsigned int t49;
unsigned int t50;
unsigned int t51;
unsigned int t52;
unsigned int t53;
unsigned int t54;
char *t55;
char *t56;
unsigned int t57;
unsigned int t58;
unsigned int t59;
unsigned int t60;
unsigned int t61;
unsigned int t62;
unsigned int t63;
unsigned int t64;
int t65;
int t66;
unsigned int t67;
unsigned int t68;
unsigned int t69;
unsigned int t70;
unsigned int t71;
unsigned int t72;
char *t73;
char *t74;
char *t75;
char *t76;
char *t77;
unsigned int t78;
unsigned int t79;
char *t80;
unsigned int t81;
unsigned int t82;
char *t83;
unsigned int t84;
unsigned int t85;
char *t86;
LAB0: t1 = (t0 + 3336U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(33, ng0);
t2 = (t0 + 2176);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = ((char*)((ng2)));
memset(t6, 0, 8);
t7 = (t4 + 4);
t8 = (t5 + 4);
t9 = *((unsigned int *)t4);
t10 = *((unsigned int *)t5);
t11 = (t9 ^ t10);
t12 = *((unsigned int *)t7);
t13 = *((unsigned int *)t8);
t14 = (t12 ^ t13);
t15 = (t11 | t14);
t16 = *((unsigned int *)t7);
t17 = *((unsigned int *)t8);
t18 = (t16 | t17);
t19 = (~(t18));
t20 = (t15 & t19);
if (t20 != 0)
goto LAB7;
LAB4: if (t18 != 0)
goto LAB6;
LAB5: *((unsigned int *)t6) = 1;
LAB7: t23 = (t0 + 1616U);
t24 = *((char **)t23);
memset(t22, 0, 8);
t23 = (t24 + 4);
t25 = *((unsigned int *)t23);
t26 = (~(t25));
t27 = *((unsigned int *)t24);
t28 = (t27 & t26);
t29 = (t28 & 1U);
if (t29 != 0)
goto LAB11;
LAB9: if (*((unsigned int *)t23) == 0)
goto LAB8;
LAB10: t30 = (t22 + 4);
*((unsigned int *)t22) = 1;
*((unsigned int *)t30) = 1;
LAB11: t31 = (t22 + 4);
t32 = (t24 + 4);
t33 = *((unsigned int *)t24);
t34 = (~(t33));
*((unsigned int *)t22) = t34;
*((unsigned int *)t31) = 0;
if (*((unsigned int *)t32) != 0)
goto LAB13;
LAB12: t39 = *((unsigned int *)t22);
*((unsigned int *)t22) = (t39 & 1U);
t40 = *((unsigned int *)t31);
*((unsigned int *)t31) = (t40 & 1U);
t42 = *((unsigned int *)t6);
t43 = *((unsigned int *)t22);
t44 = (t42 & t43);
*((unsigned int *)t41) = t44;
t45 = (t6 + 4);
t46 = (t22 + 4);
t47 = (t41 + 4);
t48 = *((unsigned int *)t45);
t49 = *((unsigned int *)t46);
t50 = (t48 | t49);
*((unsigned int *)t47) = t50;
t51 = *((unsigned int *)t47);
t52 = (t51 != 0);
if (t52 == 1)
goto LAB14;
LAB15:
LAB16: t73 = (t0 + 3752);
t74 = (t73 + 56U);
t75 = *((char **)t74);
t76 = (t75 + 56U);
t77 = *((char **)t76);
memset(t77, 0, 8);
t78 = 1U;
t79 = t78;
t80 = (t41 + 4);
t81 = *((unsigned int *)t41);
t78 = (t78 & t81);
t82 = *((unsigned int *)t80);
t79 = (t79 & t82);
t83 = (t77 + 4);
t84 = *((unsigned int *)t77);
*((unsigned int *)t77) = (t84 | t78);
t85 = *((unsigned int *)t83);
*((unsigned int *)t83) = (t85 | t79);
xsi_driver_vfirst_trans(t73, 0, 0);
t86 = (t0 + 3672);
*((int *)t86) = 1;
LAB1: return;
LAB6: t21 = (t6 + 4);
*((unsigned int *)t6) = 1;
*((unsigned int *)t21) = 1;
goto LAB7;
LAB8: *((unsigned int *)t22) = 1;
goto LAB11;
LAB13: t35 = *((unsigned int *)t22);
t36 = *((unsigned int *)t32);
*((unsigned int *)t22) = (t35 | t36);
t37 = *((unsigned int *)t31);
t38 = *((unsigned int *)t32);
*((unsigned int *)t31) = (t37 | t38);
goto LAB12;
LAB14: t53 = *((unsigned int *)t41);
t54 = *((unsigned int *)t47);
*((unsigned int *)t41) = (t53 | t54);
t55 = (t6 + 4);
t56 = (t22 + 4);
t57 = *((unsigned int *)t6);
t58 = (~(t57));
t59 = *((unsigned int *)t55);
t60 = (~(t59));
t61 = *((unsigned int *)t22);
t62 = (~(t61));
t63 = *((unsigned int *)t56);
t64 = (~(t63));
t65 = (t58 & t60);
t66 = (t62 & t64);
t67 = (~(t65));
t68 = (~(t66));
t69 = *((unsigned int *)t47);
*((unsigned int *)t47) = (t69 & t67);
t70 = *((unsigned int *)t47);
*((unsigned int *)t47) = (t70 & t68);
t71 = *((unsigned int *)t41);
*((unsigned int *)t41) = (t71 & t67);
t72 = *((unsigned int *)t41);
*((unsigned int *)t41) = (t72 & t68);
goto LAB16;
}
extern void work_m_02268563053822382377_3116099387_init()
{
static char *pe[] = {(void *)Always_25_0,(void *)Cont_33_1};
xsi_register_didat("work_m_02268563053822382377_3116099387", "isim/verkeerslicht_tb_isim_beh.exe.sim/work/m_02268563053822382377_3116099387.didat");
xsi_register_executes(pe);
}

@ -0,0 +1,177 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb.v";
static int ng1[] = {0, 0};
static int ng2[] = {1, 0};
static void Always_42_0(char *t0)
{
char t3[8];
char *t1;
char *t2;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned int t10;
unsigned int t11;
unsigned int t12;
char *t13;
char *t14;
char *t15;
unsigned int t16;
unsigned int t17;
unsigned int t18;
unsigned int t19;
unsigned int t20;
unsigned int t21;
unsigned int t22;
unsigned int t23;
char *t24;
LAB0: t1 = (t0 + 3912U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(43, ng0);
t2 = (t0 + 3720);
xsi_process_wait(t2, 500000000LL);
*((char **)t1) = &&LAB4;
LAB1: return;
LAB4: xsi_set_current_line(43, ng0);
t4 = (t0 + 2520);
t5 = (t4 + 56U);
t6 = *((char **)t5);
memset(t3, 0, 8);
t7 = (t6 + 4);
t8 = *((unsigned int *)t7);
t9 = (~(t8));
t10 = *((unsigned int *)t6);
t11 = (t10 & t9);
t12 = (t11 & 1U);
if (t12 != 0)
goto LAB8;
LAB6: if (*((unsigned int *)t7) == 0)
goto LAB5;
LAB7: t13 = (t3 + 4);
*((unsigned int *)t3) = 1;
*((unsigned int *)t13) = 1;
LAB8: t14 = (t3 + 4);
t15 = (t6 + 4);
t16 = *((unsigned int *)t6);
t17 = (~(t16));
*((unsigned int *)t3) = t17;
*((unsigned int *)t14) = 0;
if (*((unsigned int *)t15) != 0)
goto LAB10;
LAB9: t22 = *((unsigned int *)t3);
*((unsigned int *)t3) = (t22 & 1U);
t23 = *((unsigned int *)t14);
*((unsigned int *)t14) = (t23 & 1U);
t24 = (t0 + 2520);
xsi_vlogvar_assign_value(t24, t3, 0, 0, 1);
goto LAB2;
LAB5: *((unsigned int *)t3) = 1;
goto LAB8;
LAB10: t18 = *((unsigned int *)t3);
t19 = *((unsigned int *)t15);
*((unsigned int *)t3) = (t18 | t19);
t20 = *((unsigned int *)t14);
t21 = *((unsigned int *)t15);
*((unsigned int *)t14) = (t20 | t21);
goto LAB9;
}
static void Initial_47_1(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
LAB0: t1 = (t0 + 4160U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(47, ng0);
LAB4: xsi_set_current_line(49, ng0);
t2 = ((char*)((ng1)));
t3 = (t0 + 2520);
xsi_vlogvar_assign_value(t3, t2, 0, 0, 1);
xsi_set_current_line(50, ng0);
t2 = ((char*)((ng1)));
t3 = (t0 + 2680);
xsi_vlogvar_assign_value(t3, t2, 0, 0, 1);
xsi_set_current_line(51, ng0);
t2 = ((char*)((ng1)));
t3 = (t0 + 2840);
xsi_vlogvar_assign_value(t3, t2, 0, 0, 1);
xsi_set_current_line(52, ng0);
t2 = ((char*)((ng1)));
t3 = (t0 + 3000);
xsi_vlogvar_assign_value(t3, t2, 0, 0, 1);
xsi_set_current_line(55, ng0);
t2 = ((char*)((ng2)));
t3 = (t0 + 2680);
xsi_vlogvar_assign_value(t3, t2, 0, 0, 1);
xsi_set_current_line(56, ng0);
t2 = (t0 + 3968);
xsi_process_wait(t2, 500000000LL);
*((char **)t1) = &&LAB5;
LAB1: return;
LAB5: xsi_set_current_line(56, ng0);
t3 = ((char*)((ng1)));
t4 = (t0 + 2680);
xsi_vlogvar_assign_value(t4, t3, 0, 0, 1);
goto LAB1;
}
extern void work_m_08900781484644397074_2259196339_init()
{
static char *pe[] = {(void *)Always_42_0,(void *)Initial_47_1};
xsi_register_didat("work_m_08900781484644397074_2259196339", "isim/verkeerslicht_tb_isim_beh.exe.sim/work/m_08900781484644397074_2259196339.didat");
xsi_register_executes(pe);
}

@ -0,0 +1,337 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/glbl.v";
static unsigned int ng1[] = {1U, 0U};
static unsigned int ng2[] = {0U, 0U};
static void NetDecl_16_0(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
char *t10;
unsigned int t11;
unsigned int t12;
char *t13;
unsigned int t14;
unsigned int t15;
char *t16;
LAB0: t1 = (t0 + 6952U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(16, ng0);
t2 = (t0 + 1960U);
t3 = *((char **)t2);
t2 = (t0 + 8640);
t4 = (t2 + 56U);
t5 = *((char **)t4);
t6 = (t5 + 56U);
t7 = *((char **)t6);
memset(t7, 0, 8);
t8 = 1U;
t9 = t8;
t10 = (t3 + 4);
t11 = *((unsigned int *)t3);
t8 = (t8 & t11)