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- trade off beter uitleggen: grootte lichtbron, pixel footprint |
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- geen functienamen uit code gebruiken |
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Subproject commit e57549f13fe7787d572adcf07d70ac4dd8f1dd40 |
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Subproject commit 12e8b4884e0ad2f4745b5898e8d508e0dd4c750d |
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build: |
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pandoc -t pdf -o verslag.pdf verslag.md
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--- |
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title: 'Digitale electronica en processoren: practicum 1' |
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geometry: margin=2cm |
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author: |
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- Daan Vanoverloop |
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--- |
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|
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# Verilog beschrijving |
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|
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```verilog |
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`timescale 1ns / 1ns |
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////////////////////////////////////////////////////////////////////////////////// |
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// Company: KU Leuven |
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// Module Name: verkeerslicht |
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// Project Name: verkeerslicht |
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// Revision 0.01 - File Created |
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// Additional notes: |
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// - Parameter BASE_FREQ is added to speed up simulation |
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// - Assumption: 2*FREQ <= BASE_FREQ <= 50000000 (default, Xilinx clock) |
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////////////////////////////////////////////////////////////////////////////////// |
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module verkeerslicht( |
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input clk, |
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input reset, |
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input voet, |
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input auto, |
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output reg hw_g, |
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output reg hw_o, |
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output reg hw_r, |
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output reg zs_g, |
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output reg zs_o, |
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output reg zs_r |
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); |
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// Parameter om simulatie te kunnen versnellen |
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parameter BASE_FREQ = 50_000_000; // 50 Mhz Xilinx klok |
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|
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// Gereduceerde klokfrequentie (100 Hz) op 'ce' (clock enable). |
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// Enkel te gebuiken samen met clk! |
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parameter FREQ = 100; |
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wire ce; |
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prescaler #(.new_freq(FREQ), .old_freq(BASE_FREQ)) maak_ce (clk, reset, ce); |
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|
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// Teller voor lichten |
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reg [8:0] Q; |
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reg herstart_teller = 1'b0; |
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always @(posedge clk, posedge reset) begin |
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if (reset) |
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Q <= 0; |
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else if (ce) |
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Q <= herstart_teller? 0: Q + 1; |
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end |
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|
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// Timing lichten: parameters M_HWG, M_ZSG, M_O, M_R |
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// M_* = maximum tellerwaarde voor * |
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parameter M_HWG = 400; |
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parameter M_ZSG = 200; |
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parameter M_O = 100; |
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parameter M_R = 100; |
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|
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// Definitie toestanden |
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// Kies als reset-toestand een veilige toestand (HW en ZS rood), |
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// waarbij daarna men zo snel mogelijk naar groen op HW gaat. |
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|
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reg [2:0] CurrentState, NextState; |
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parameter HW_G = 3'b000; |
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parameter HW_O = 3'b001; |
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parameter HW_R = 3'b011; |
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parameter ZS_G = 3'b111; |
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parameter ZS_O = 3'b101; |
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parameter ZS_R = 3'b100; |
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|
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initial CurrentState = ZS_R; |
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|
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// Knop voetgangers |
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|
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|
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// State register |
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always @(posedge clk, posedge reset) |
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if (reset) |
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CurrentState <= ZS_R; |
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else |
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CurrentState <= NextState; |
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|
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// Next state logic |
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always @(CurrentState, posedge Q, posedge ce) begin |
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if (ce == 1) |
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case (CurrentState) |
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HW_G: if (Q < M_HWG) |
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NextState = HW_G; |
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else |
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NextState = HW_O; |
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HW_O: if (Q < M_O) |
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NextState = HW_O; |
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else |
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NextState = HW_R; |
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HW_R: if (Q < M_R) |
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NextState = HW_R; |
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else |
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NextState = ZS_G; |
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ZS_G: if (Q < M_ZSG) |
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NextState = ZS_G; |
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else |
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NextState = ZS_O; |
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ZS_O: if (Q < M_O) |
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NextState = ZS_O; |
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else |
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NextState = ZS_R; |
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ZS_R: if (Q < M_R) |
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NextState = ZS_R; |
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else |
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NextState = HW_G; |
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default: NextState = ZS_R; |
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endcase |
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|
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if (CurrentState != NextState) |
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herstart_teller = 1; |
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else |
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herstart_teller = 0; |
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end |
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|
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// Output logic |
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always @(CurrentState) begin |
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herstart_teller = 1; |
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hw_g = 0; |
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hw_o = 0; |
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hw_r = 0; |
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zs_g = 0; |
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zs_o = 0; |
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zs_r = 0; |
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|
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case (CurrentState) |
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HW_G: begin |
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hw_g = 1; |
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zs_r = 1; |
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end |
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HW_O: begin |
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hw_o = 1; |
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zs_r = 1; |
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end |
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HW_R: begin |
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hw_r = 1; |
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zs_r = 1; |
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end |
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ZS_G: begin |
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hw_r = 1; |
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zs_g = 1; |
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end |
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ZS_O: begin |
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hw_r = 1; |
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zs_o = 1; |
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end |
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ZS_R: begin |
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hw_r = 1; |
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zs_r = 1; |
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end |
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default: ; |
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endcase |
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end |
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|
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endmodule |
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``` |
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|
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# Simulatieresultaten |
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|
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In deze sectie wordt het simulatieresultaat van het verkeerslicht gegeven. Er was geen tijd om de geavanceerde aansturing te implementeren. |
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Als stimulus werd het reset signaal voor een korte periode op $1$ gezet. |
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|
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 |
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|
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Hierop is duidelijk zichtbaar dat de verkeerslichten nooit tegelijkertijd groen zijn en dat een verkeerslicht eerst oranje wordt voordat het rood wordt. |
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|
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# Bespreking |
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|
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Bij de implementatie had ik wat moeite met de code voor `herstart_teller`. Dit zou eigenlijk in de output logic moeten, maar deze hangt niet af van de huidige toestand, |
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maar van de overgang van een toestand naar een andere toestand. Daarom heb ik deze in de next state logic gezet, zodat deze op $1$ gezet wordt wanneer de toestand |
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verandert naar een andere toestand. |
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|
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Voor de output logic heb ik ervoor gekozen om alle output variabelen eerst op $0$ te zetten en dan in de case statement de variabelen die op $1$ moeten staan |
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op $1$ zetten. Zo moet ik niet in elke branch herhalen dat alle andere variabelen op $0$ moeten staan. |
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<?xml version="1.0" encoding="UTF-8"?> |
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<!-- IMPORTANT: This is an internal file that has been generated --> |
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<!-- by the Xilinx ISE software. Any direct editing or --> |
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<!-- changes made to this file may result in unpredictable --> |
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<!-- behavior or data corruption. It is strongly advised that --> |
||||
<!-- users do not edit the contents of this file. --> |
||||
<!-- --> |
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> |
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|
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<messages> |
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<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht.v" into library work</arg> |
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</msg> |
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|
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</messages> |
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|
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@ -0,0 +1,10 @@ |
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net "clk" loc="T9"; |
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net "reset" loc="L14"; |
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net "hw_g" loc="P11"; |
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net "hw_o" loc="P12"; |
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net "hw_r" loc="N12"; |
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net "zs_g" loc="P13"; |
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net "zs_o" loc="N14"; |
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net "zs_r" loc="L12"; |
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net "voet" loc="L13"; |
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net "auto" loc="K13"; |
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@ -0,0 +1,23 @@ |
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Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -o "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb_isim_beh.exe" -prj "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb_beh.prj" "work.verkeerslicht_tb" "work.glbl" |
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ISim P.20131013 (signature 0xfbc00daa) |
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Number of CPUs detected in this system: 8 |
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Turning on mult-threading, number of parallel sub-compilation jobs: 16 |
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Determining compilation order of HDL files |
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Analyzing Verilog file "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/prescaler.v" into library work |
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Analyzing Verilog file "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht.v" into library work |
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Analyzing Verilog file "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb.v" into library work |
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Analyzing Verilog file "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work |
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Starting static elaboration |
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Completed static elaboration |
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Fuse Memory Usage: 82476 KB |
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Fuse CPU Usage: 1160 ms |
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Compiling module prescaler(new_freq=100,old_freq=... |
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Compiling module verkeerslicht(BASE_FREQ=1000) |
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Compiling module verkeerslicht_tb |
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Compiling module glbl |
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Time Resolution for simulation is 1ps. |
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Compiled 4 Verilog Units |
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Built simulation executable /var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb_isim_beh.exe |
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Fuse Memory Usage: 1167000 KB |
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Fuse CPU Usage: 1170 ms |
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GCC CPU Usage: 200 ms |
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@ -0,0 +1,9 @@ |
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<?xml version="1.0" encoding="UTF-8"?> |
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<!-- IMPORTANT: This is an internal file that has been generated |
||||
by the Xilinx ISE software. Any direct editing or |
||||
changes made to this file may result in unpredictable |
||||
behavior or data corruption. It is strongly advised that |
||||
users do not edit the contents of this file. --> |
||||
<messages> |
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</messages> |
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|
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@ -0,0 +1 @@ |
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-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -o "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb_isim_beh.exe" -prj "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb_beh.prj" "work.verkeerslicht_tb" "work.glbl" |
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@ -0,0 +1,117 @@ |
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<?xml version='1.0' encoding='utf-8'?> |
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<!--This is an ISE project configuration file.--> |
||||
<!--It holds project specific layout data for the projectmgr plugin.--> |
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<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.--> |
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<Project version="2" owner="projectmgr" name="verkeerslicht" > |
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<!--This is an ISE project configuration file.--> |
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<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" > |
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<ClosedNodes> |
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<ClosedNodesVersion>2</ClosedNodesVersion> |
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</ClosedNodes> |
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<SelectedItems> |
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<SelectedItem>verkeerslicht (/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht.v)</SelectedItem> |
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
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<CurrentItem>verkeerslicht (/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht.v)</CurrentItem> |
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</ItemView> |
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<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" > |
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<ClosedNodes> |
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<ClosedNodesVersion>1</ClosedNodesVersion> |
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<ClosedNode>Configure Target Device</ClosedNode> |
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<ClosedNode>Design Utilities</ClosedNode> |
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<ClosedNode>Implement Design</ClosedNode> |
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<ClosedNode>Synthesize - XST</ClosedNode> |
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</viewgroup> |
||||
<viewgroup label="XPS Errors and Warnings" > |
||||
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" /> |
||||
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" /> |
||||
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" /> |
||||
</viewgroup> |
||||
<viewgroup label="XPS Reports" > |
||||
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" /> |
||||
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> |
||||
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> |
||||
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="verkeerslicht.log" label="System Log File" /> |
||||
</viewgroup> |
||||
<viewgroup label="Errors and Warnings" > |
||||
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" /> |
||||
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" /> |
||||
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" /> |
||||
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" /> |
||||
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" /> |
||||
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" /> |
||||
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" /> |
||||
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" /> |
||||
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" /> |
||||
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" /> |
||||
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" /> |
||||
</viewgroup> |
||||
<viewgroup label="Detailed Reports" > |
||||
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="verkeerslicht.syr" label="Synthesis Report" > |
||||
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" /> |
||||
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " /> |
||||
<toc-item title="HDL Compilation" target=" HDL Compilation " /> |
||||
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> |
||||
<toc-item title="HDL Analysis" target=" HDL Analysis " /> |
||||
<toc-item title="HDL Parsing" target=" HDL Parsing " /> |
||||
<toc-item title="HDL Elaboration" target=" HDL Elaboration " /> |
||||
<toc-item title="HDL Synthesis" target=" HDL Synthesis " /> |
||||
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" /> |
||||
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" /> |
||||
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" /> |
||||
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " /> |
||||
<toc-item title="Partition Report" target=" Partition Report " /> |
||||
<toc-item title="Final Report" target=" Final Report " /> |
||||
<toc-item title="Design Summary" target=" Design Summary " /> |
||||
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" /> |
||||
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" /> |
||||
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" /> |
||||
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" /> |
||||
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" /> |
||||
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" /> |
||||
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" /> |
||||
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" /> |
||||
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" /> |
||||
</view> |
||||
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="verkeerslicht.srr" label="Synplify Report" /> |
||||
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="verkeerslicht.prec_log" label="Precision Report" /> |
||||
<view inputState="Synthesized" program="ngdbuild" type="Report" file="verkeerslicht.bld" label="Translation Report" > |
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
||||
<toc-item title="Command Line" target="Command Line:" /> |
||||
<toc-item title="Partition Status" target="Partition Implementation Status" /> |
||||
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" /> |
||||
</view> |
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="verkeerslicht_map.mrp" label="Map Report" > |
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
||||
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" /> |
||||
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" /> |
||||
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" /> |
||||
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" /> |
||||
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" /> |
||||
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" /> |
||||
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" /> |
||||
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" /> |
||||
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" /> |
||||
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" /> |
||||
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" /> |
||||
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" /> |
||||
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" /> |
||||
</view> |
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="verkeerslicht.par" label="Place and Route Report" > |
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
||||
<toc-item title="Device Utilization" target="Device Utilization Summary:" /> |
||||
<toc-item title="Router Information" target="Starting Router" /> |
||||
<toc-item title="Partition Status" target="Partition Implementation Status" /> |
||||
<toc-item title="Clock Report" target="Generating Clock Report" /> |
||||
<toc-item title="Timing Results" target="Timing Score:" /> |
||||
<toc-item title="Final Summary" target="Peak Memory Usage:" /> |
||||
</view> |
||||
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="verkeerslicht.twr" label="Post-PAR Static Timing Report" > |
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
||||
<toc-item title="Timing Report Description" target="Device,package,speed:" /> |
||||
<toc-item title="Informational Messages" target="INFO:" /> |
||||
<toc-item title="Warning Messages" target="WARNING:" /> |
||||
<toc-item title="Timing Constraints" target="Timing constraint:" /> |
||||
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> |
||||
<toc-item title="Data Sheet Report" target="Data Sheet report:" /> |
||||
<toc-item title="Timing Summary" target="Timing summary:" /> |
||||
<toc-item title="Trace Settings" target="Trace Settings:" /> |
||||
</view> |
||||
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="verkeerslicht.rpt" label="CPLD Fitter Report (Text)" > |
||||
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" /> |
||||
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" /> |
||||
<toc-item title="Pin Resources" target="** Pin Resources **" /> |
||||
<toc-item title="Global Resources" target="** Global Control Resources **" /> |
||||
</view> |
||||
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="verkeerslicht.tim" label="CPLD Timing Report (Text)" > |
||||
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" /> |
||||
<toc-item title="Performance Summary" target="Performance Summary:" /> |
||||
</view> |
||||
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="verkeerslicht.pwr" label="Power Report" > |
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
||||
<toc-item title="Power summary" target="Power summary" /> |
||||
<toc-item title="Thermal summary" target="Thermal summary" /> |
||||
</view> |
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="verkeerslicht.bgn" label="Bitgen Report" > |
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
||||
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> |
||||
<toc-item title="Final Summary" target="DRC detected" /> |
||||
</view> |
||||
</viewgroup> |
||||
<viewgroup label="Secondary Reports" > |
||||
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> |
||||
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/verkeerslicht_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > |
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
||||
</view> |
||||
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/verkeerslicht_translate.nlf" label="Post-Translate Simulation Model Report" > |
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
||||
</view> |
||||
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="verkeerslicht_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> |
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="verkeerslicht_map.map" label="Map Log File" > |
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
||||
<toc-item title="Design Information" target="Design Information" /> |
||||
<toc-item title="Design Summary" target="Design Summary" /> |
||||
</view> |
||||
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" /> |
||||
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="verkeerslicht_preroute.twr" label="Post-Map Static Timing Report" > |
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
||||
<toc-item title="Timing Report Description" target="Device,package,speed:" /> |
||||
<toc-item title="Informational Messages" target="INFO:" /> |
||||
<toc-item title="Warning Messages" target="WARNING:" /> |
||||
<toc-item title="Timing Constraints" target="Timing constraint:" /> |
||||
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> |
||||
<toc-item title="Data Sheet Report" target="Data Sheet report:" /> |
||||
<toc-item title="Timing Summary" target="Timing summary:" /> |
||||
<toc-item title="Trace Settings" target="Trace Settings:" /> |
||||
</view> |
||||
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/verkeerslicht_map.nlf" label="Post-Map Simulation Model Report" /> |
||||
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="verkeerslicht_map.psr" label="Physical Synthesis Report" > |
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
||||
</view> |
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="verkeerslicht_pad.txt" label="Pad Report" > |
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
||||
</view> |
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="verkeerslicht.unroutes" label="Unroutes Report" > |
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
||||
</view> |
||||
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="verkeerslicht_preroute.tsi" label="Post-Map Constraints Interaction Report" > |
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
||||
</view> |
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="verkeerslicht.grf" label="Guide Results Report" /> |
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="verkeerslicht.dly" label="Asynchronous Delay Report" /> |
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="verkeerslicht.clk_rgn" label="Clock Region Report" /> |
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="verkeerslicht.tsi" label="Post-Place and Route Constraints Interaction Report" > |
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
||||
</view> |
||||
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="verkeerslicht_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" /> |
||||
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/verkeerslicht_timesim.nlf" label="Post-Place and Route Simulation Model Report" /> |
||||
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="verkeerslicht_sta.nlf" label="Primetime Netlist Report" > |
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
||||
</view> |
||||
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="verkeerslicht.ibs" label="IBIS Model" > |
||||
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" /> |
||||
<toc-item title="Component" target="Component " /> |
||||
</view> |
||||
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="verkeerslicht.lck" label="Back-annotate Pin Report" > |
||||
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" /> |
||||
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" /> |
||||
</view> |
||||
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="verkeerslicht.lpc" label="Locked Pin Constraints" > |
||||
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" /> |
||||
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> |
||||
</view> |
||||
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/verkeerslicht_timesim.nlf" label="Post-Fit Simulation Model Report" /> |
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" /> |
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" /> |
||||
</viewgroup> |
||||
</body> |
||||
</report-views> |
||||
@ -0,0 +1,3 @@ |
||||
onerror {resume} |
||||
wave add / |
||||
run 35 sec; |
||||
@ -0,0 +1,22 @@ |
||||
ISim log file |
||||
Running: /var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb_isim_beh.wdb |
||||
ISim P.20131013 (signature 0xfbc00daa) |
||||
WARNING: A WEBPACK license was found. |
||||
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
||||
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
||||
This is a Lite version of ISim. |
||||
Time resolution is 1 ps |
||||
# onerror resume |
||||
# wave add / |
||||
# run 35 sec |
||||
Simulator is doing circuit initialization process. |
||||
Finished circuit initialization process. |
||||
ISim P.20131013 (signature 0xfbc00daa) |
||||
WARNING: A WEBPACK license was found. |
||||
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
||||
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
||||
This is a Lite version of ISim. |
||||
# run 35 sec |
||||
Simulator is doing circuit initialization process. |
||||
Finished circuit initialization process. |
||||
# exit 0 |
||||
@ -0,0 +1,16 @@ |
||||
<TABLE BORDER CELLSPACING=0 WIDTH='100%'> |
||||
<xtag-section name="ISimStatistics"> |
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR> |
||||
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value></xtag-isim-property-value></TD></TR> |
||||
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>1170 ms, 1167000 KB</xtag-isim-property-value></TD></TR> |
||||
|
||||
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>27</xtag-isim-property-value></TD></TR> |
||||
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>24</xtag-isim-property-value></TD></TR> |
||||
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>4</xtag-isim-property-value></TD></TR> |
||||
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>25</xtag-isim-property-value></TD></TR> |
||||
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>35 s</xtag-isim-property-value></TD></TR> |
||||
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.11 sec, 258207 KB</xtag-isim-property-value></TD></TR> |
||||
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR> |
||||
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR> |
||||
</xtag-section> |
||||
</TABLE> |
||||
@ -0,0 +1 @@ |
||||
14.7 |
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -0,0 +1,29 @@ |
||||
Command line: |
||||
verkeerslicht_tb_isim_beh.exe |
||||
-simmode gui |
||||
-simrunnum 0 |
||||
-socket 38431 |
||||
|
||||
Fri Apr 29 12:58:02 2022 |
||||
|
||||
|
||||
Elaboration Time: 0.02 sec |
||||
|
||||
Current Memory Usage: 183.759 Meg |
||||
|
||||
Total Signals : 27 |
||||
Total Nets : 24 |
||||
Total Signal Drivers : 16 |
||||
Total Blocks : 4 |
||||
Total Primitive Blocks : 2 |
||||
Total Processes : 25 |
||||
Total Traceable Variables : 50 |
||||
Total Scalar Nets and Variables : 525 |
||||
Total Line Count : 91 |
||||
|
||||
Total Simulation Time: 0.11 sec |
||||
|
||||
Current Memory Usage: 259.26 Meg |
||||
|
||||
Fri Apr 29 13:28:57 2022 |
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -0,0 +1,365 @@ |
||||
/**********************************************************************/ |
||||
/* ____ ____ */ |
||||
/* / /\/ / */ |
||||
/* /___/ \ / */ |
||||
/* \ \ \/ */ |
||||
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ |
||||
/* / / All Right Reserved. */ |
||||
/* /---/ /\ */ |
||||
/* \ \ / \ */ |
||||
/* \___\/\___\ */ |
||||
/***********************************************************************/ |
||||
|
||||
/* This file is designed for use with ISim build 0xfbc00daa */ |
||||
|
||||
#define XSI_HIDE_SYMBOL_SPEC true |
||||
#include "xsi.h" |
||||
#include <memory.h> |
||||
#ifdef __GNUC__ |
||||
#include <stdlib.h> |
||||
#else |
||||
#include <malloc.h> |
||||
#define alloca _alloca |
||||
#endif |
||||
static const char *ng0 = "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/prescaler.v"; |
||||
static int ng1[] = {1, 0}; |
||||
static int ng2[] = {0, 0}; |
||||
|
||||
|
||||
|
||||
static void Always_25_0(char *t0) |
||||
{ |
||||
char t15[8]; |
||||
char *t1; |
||||
char *t2; |
||||
char *t3; |
||||
char *t4; |
||||
char *t5; |
||||
unsigned int t6; |
||||
unsigned int t7; |
||||
unsigned int t8; |
||||
unsigned int t9; |
||||
unsigned int t10; |
||||
char *t11; |
||||
char *t12; |
||||
char *t13; |
||||
char *t14; |
||||
char *t16; |
||||
|
||||
LAB0: t1 = (t0 + 3088U); |
||||
t2 = *((char **)t1); |
||||
if (t2 == 0) |
||||
goto LAB2; |
||||
|
||||
LAB3: goto *t2; |
||||
|
||||
LAB2: xsi_set_current_line(25, ng0); |
||||
t2 = (t0 + 3656); |
||||
*((int *)t2) = 1; |
||||
t3 = (t0 + 3120); |
||||
*((char **)t3) = t2; |
||||
*((char **)t1) = &&LAB4; |
||||
|
||||
LAB1: return; |
||||
LAB4: xsi_set_current_line(26, ng0); |
||||
t4 = (t0 + 1616U); |
||||
t5 = *((char **)t4); |
||||
t4 = (t5 + 4); |
||||
t6 = *((unsigned int *)t4); |
||||
t7 = (~(t6)); |
||||
t8 = *((unsigned int *)t5); |
||||
t9 = (t8 & t7); |
||||
t10 = (t9 != 0); |
||||
if (t10 > 0) |
||||
goto LAB5; |
||||
|
||||
LAB6: xsi_set_current_line(28, ng0); |
||||
t2 = (t0 + 2176); |
||||
t3 = (t2 + 56U); |
||||
t4 = *((char **)t3); |
||||
t5 = (t4 + 4); |
||||
t6 = *((unsigned int *)t5); |
||||
t7 = (~(t6)); |
||||
t8 = *((unsigned int *)t4); |
||||
t9 = (t8 & t7); |
||||
t10 = (t9 != 0); |
||||
if (t10 > 0) |
||||
goto LAB8; |
||||
|
||||
LAB9: xsi_set_current_line(31, ng0); |
||||
t2 = (t0 + 744); |
||||
t3 = *((char **)t2); |
||||
t2 = (t0 + 2176); |
||||
xsi_vlogvar_wait_assign_value(t2, t3, 0, 0, 25, 0LL); |
||||
|
||||
LAB10: |
||||
LAB7: goto LAB2; |
||||
|
||||
LAB5: xsi_set_current_line(27, ng0); |
||||
t11 = (t0 + 744); |
||||
t12 = *((char **)t11); |
||||
t11 = (t0 + 2176); |
||||
xsi_vlogvar_wait_assign_value(t11, t12, 0, 0, 25, 0LL); |
||||
goto LAB7; |
||||
|
||||
LAB8: xsi_set_current_line(29, ng0); |
||||
t11 = (t0 + 2176); |
||||
t12 = (t11 + 56U); |
||||
t13 = *((char **)t12); |
||||
t14 = ((char*)((ng1))); |
||||
memset(t15, 0, 8); |
||||
xsi_vlog_unsigned_minus(t15, 32, t13, 25, t14, 32); |
||||
t16 = (t0 + 2176); |
||||
xsi_vlogvar_wait_assign_value(t16, t15, 0, 0, 25, 0LL); |
||||
goto LAB10; |
||||
|
||||
} |
||||
|
||||
static void Cont_33_1(char *t0) |
||||
{ |
||||
char t6[8]; |
||||
char t22[8]; |
||||
char t41[8]; |
||||
char *t1; |
||||
char *t2; |
||||
char *t3; |
||||
char *t4; |
||||
char *t5; |
||||
char *t7; |
||||
char *t8; |
||||
unsigned int t9; |
||||
unsigned int t10; |
||||
unsigned int t11; |
||||
unsigned int t12; |
||||
unsigned int t13; |
||||
unsigned int t14; |
||||
unsigned int t15; |
||||
unsigned int t16; |
||||
unsigned int t17; |
||||
unsigned int t18; |
||||
unsigned int t19; |
||||
unsigned int t20; |
||||
char *t21; |
||||
char *t23; |
||||
char *t24; |
||||
unsigned int t25; |
||||
unsigned int t26; |
||||
unsigned int t27; |
||||
unsigned int t28; |
||||
unsigned int t29; |
||||
char *t30; |
||||
char *t31; |
||||
char *t32; |
||||
unsigned int t33; |
||||
unsigned int t34; |
||||
unsigned int t35; |
||||
unsigned int t36; |
||||
unsigned int t37; |
||||
unsigned int t38; |
||||
unsigned int t39; |
||||
unsigned int t40; |
||||
unsigned int t42; |
||||
unsigned int t43; |
||||
unsigned int t44; |
||||
char *t45; |
||||
char *t46; |
||||
char *t47; |
||||
unsigned int t48; |
||||
unsigned int t49; |
||||
unsigned int t50; |
||||
unsigned int t51; |
||||
unsigned int t52; |
||||
unsigned int t53; |
||||
unsigned int t54; |
||||
char *t55; |
||||
char *t56; |
||||
unsigned int t57; |
||||
unsigned int t58; |
||||
unsigned int t59; |
||||
unsigned int t60; |
||||
unsigned int t61; |
||||
unsigned int t62; |
||||
unsigned int t63; |
||||
unsigned int t64; |
||||
int t65; |
||||
int t66; |
||||
unsigned int t67; |
||||
unsigned int t68; |
||||
unsigned int t69; |
||||
unsigned int t70; |
||||
unsigned int t71; |
||||
unsigned int t72; |
||||
char *t73; |
||||
char *t74; |
||||
char *t75; |
||||
char *t76; |
||||
char *t77; |
||||
unsigned int t78; |
||||
unsigned int t79; |
||||
char *t80; |
||||
unsigned int t81; |
||||
unsigned int t82; |
||||
char *t83; |
||||
unsigned int t84; |
||||
unsigned int t85; |
||||
char *t86; |
||||
|
||||
LAB0: t1 = (t0 + 3336U); |
||||
t2 = *((char **)t1); |
||||
if (t2 == 0) |
||||
goto LAB2; |
||||
|
||||
LAB3: goto *t2; |
||||
|
||||
LAB2: xsi_set_current_line(33, ng0); |
||||
t2 = (t0 + 2176); |
||||
t3 = (t2 + 56U); |
||||
t4 = *((char **)t3); |
||||
t5 = ((char*)((ng2))); |
||||
memset(t6, 0, 8); |
||||
t7 = (t4 + 4); |
||||
t8 = (t5 + 4); |
||||
t9 = *((unsigned int *)t4); |
||||
t10 = *((unsigned int *)t5); |
||||
t11 = (t9 ^ t10); |
||||
t12 = *((unsigned int *)t7); |
||||
t13 = *((unsigned int *)t8); |
||||
t14 = (t12 ^ t13); |
||||
t15 = (t11 | t14); |
||||
t16 = *((unsigned int *)t7); |
||||
t17 = *((unsigned int *)t8); |
||||
t18 = (t16 | t17); |
||||
t19 = (~(t18)); |
||||
t20 = (t15 & t19); |
||||
if (t20 != 0) |
||||
goto LAB7; |
||||
|
||||
LAB4: if (t18 != 0) |
||||
goto LAB6; |
||||
|
||||
LAB5: *((unsigned int *)t6) = 1; |
||||
|
||||
LAB7: t23 = (t0 + 1616U); |
||||
t24 = *((char **)t23); |
||||
memset(t22, 0, 8); |
||||
t23 = (t24 + 4); |
||||
t25 = *((unsigned int *)t23); |
||||
t26 = (~(t25)); |
||||
t27 = *((unsigned int *)t24); |
||||
t28 = (t27 & t26); |
||||
t29 = (t28 & 1U); |
||||
if (t29 != 0) |
||||
goto LAB11; |
||||
|
||||
LAB9: if (*((unsigned int *)t23) == 0) |
||||
goto LAB8; |
||||
|
||||
LAB10: t30 = (t22 + 4); |
||||
*((unsigned int *)t22) = 1; |
||||
*((unsigned int *)t30) = 1; |
||||
|
||||
LAB11: t31 = (t22 + 4); |
||||
t32 = (t24 + 4); |
||||
t33 = *((unsigned int *)t24); |
||||
t34 = (~(t33)); |
||||
*((unsigned int *)t22) = t34; |
||||
*((unsigned int *)t31) = 0; |
||||
if (*((unsigned int *)t32) != 0) |
||||
goto LAB13; |
||||
|
||||
LAB12: t39 = *((unsigned int *)t22); |
||||
*((unsigned int *)t22) = (t39 & 1U); |
||||
t40 = *((unsigned int *)t31); |
||||
*((unsigned int *)t31) = (t40 & 1U); |
||||
t42 = *((unsigned int *)t6); |
||||
t43 = *((unsigned int *)t22); |
||||
t44 = (t42 & t43); |
||||
*((unsigned int *)t41) = t44; |
||||
t45 = (t6 + 4); |
||||
t46 = (t22 + 4); |
||||
t47 = (t41 + 4); |
||||
t48 = *((unsigned int *)t45); |
||||
t49 = *((unsigned int *)t46); |
||||
t50 = (t48 | t49); |
||||
*((unsigned int *)t47) = t50; |
||||
t51 = *((unsigned int *)t47); |
||||
t52 = (t51 != 0); |
||||
if (t52 == 1) |
||||
goto LAB14; |
||||
|
||||
LAB15: |
||||
LAB16: t73 = (t0 + 3752); |
||||
t74 = (t73 + 56U); |
||||
t75 = *((char **)t74); |
||||
t76 = (t75 + 56U); |
||||
t77 = *((char **)t76); |
||||
memset(t77, 0, 8); |
||||
t78 = 1U; |
||||
t79 = t78; |
||||
t80 = (t41 + 4); |
||||
t81 = *((unsigned int *)t41); |
||||
t78 = (t78 & t81); |
||||
t82 = *((unsigned int *)t80); |
||||
t79 = (t79 & t82); |
||||
t83 = (t77 + 4); |
||||
t84 = *((unsigned int *)t77); |
||||
*((unsigned int *)t77) = (t84 | t78); |
||||
t85 = *((unsigned int *)t83); |
||||
*((unsigned int *)t83) = (t85 | t79); |
||||
xsi_driver_vfirst_trans(t73, 0, 0); |
||||
t86 = (t0 + 3672); |
||||
*((int *)t86) = 1; |
||||
|
||||
LAB1: return; |
||||
LAB6: t21 = (t6 + 4); |
||||
*((unsigned int *)t6) = 1; |
||||
*((unsigned int *)t21) = 1; |
||||
goto LAB7; |
||||
|
||||
LAB8: *((unsigned int *)t22) = 1; |
||||
goto LAB11; |
||||
|
||||
LAB13: t35 = *((unsigned int *)t22); |
||||
t36 = *((unsigned int *)t32); |
||||
*((unsigned int *)t22) = (t35 | t36); |
||||
t37 = *((unsigned int *)t31); |
||||
t38 = *((unsigned int *)t32); |
||||
*((unsigned int *)t31) = (t37 | t38); |
||||
goto LAB12; |
||||
|
||||
LAB14: t53 = *((unsigned int *)t41); |
||||
t54 = *((unsigned int *)t47); |
||||
*((unsigned int *)t41) = (t53 | t54); |
||||
t55 = (t6 + 4); |
||||
t56 = (t22 + 4); |
||||
t57 = *((unsigned int *)t6); |
||||
t58 = (~(t57)); |
||||
t59 = *((unsigned int *)t55); |
||||
t60 = (~(t59)); |
||||
t61 = *((unsigned int *)t22); |
||||
t62 = (~(t61)); |
||||
t63 = *((unsigned int *)t56); |
||||
t64 = (~(t63)); |
||||
t65 = (t58 & t60); |
||||
t66 = (t62 & t64); |
||||
t67 = (~(t65)); |
||||
t68 = (~(t66)); |
||||
t69 = *((unsigned int *)t47); |
||||
*((unsigned int *)t47) = (t69 & t67); |
||||
t70 = *((unsigned int *)t47); |
||||
*((unsigned int *)t47) = (t70 & t68); |
||||
t71 = *((unsigned int *)t41); |
||||
*((unsigned int *)t41) = (t71 & t67); |
||||
t72 = *((unsigned int *)t41); |
||||
*((unsigned int *)t41) = (t72 & t68); |
||||
goto LAB16; |
||||
|
||||
} |
||||
|
||||
|
||||
extern void work_m_02268563053822382377_3116099387_init() |
||||
{ |
||||
static char *pe[] = {(void *)Always_25_0,(void *)Cont_33_1}; |
||||
xsi_register_didat("work_m_02268563053822382377_3116099387", "isim/verkeerslicht_tb_isim_beh.exe.sim/work/m_02268563053822382377_3116099387.didat"); |
||||
xsi_register_executes(pe); |
||||
} |
||||
Binary file not shown.
Binary file not shown.
@ -0,0 +1,177 @@ |
||||
/**********************************************************************/ |
||||
/* ____ ____ */ |
||||
/* / /\/ / */ |
||||
/* /___/ \ / */ |
||||
/* \ \ \/ */ |
||||
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ |
||||
/* / / All Right Reserved. */ |
||||
/* /---/ /\ */ |
||||
/* \ \ / \ */ |
||||
/* \___\/\___\ */ |
||||
/***********************************************************************/ |
||||
|
||||
/* This file is designed for use with ISim build 0xfbc00daa */ |
||||
|
||||
#define XSI_HIDE_SYMBOL_SPEC true |
||||
#include "xsi.h" |
||||
#include <memory.h> |
||||
#ifdef __GNUC__ |
||||
#include <stdlib.h> |
||||
#else |
||||
#include <malloc.h> |
||||
#define alloca _alloca |
||||
#endif |
||||
static const char *ng0 = "/var/home/daan/Documents/School/Digitale elektronica en processoren/verkeerslicht/verkeerslicht_tb.v"; |
||||
static int ng1[] = {0, 0}; |
||||
static int ng2[] = {1, 0}; |
||||
|
||||
|
||||
|
||||
static void Always_42_0(char *t0) |
||||
{ |
||||
char t3[8]; |
||||
char *t1; |
||||
char *t2; |
||||
char *t4; |
||||
char *t5; |
||||
char *t6; |
||||
char *t7; |
||||
unsigned int t8; |
||||
unsigned int t9; |
||||
unsigned int t10; |
||||
unsigned int t11; |
||||
unsigned int t12; |
||||
char *t13; |
||||
char *t14; |
||||
char *t15; |
||||
unsigned int t16; |
||||
unsigned int t17; |
||||
unsigned int t18; |
||||
unsigned int t19; |
||||
unsigned int t20; |
||||
unsigned int t21; |
||||
unsigned int t22; |
||||
unsigned int t23; |
||||
char *t24; |
||||
|
||||
LAB0: t1 = (t0 + 3912U); |
||||
t2 = *((char **)t1); |
||||
if (t2 == 0) |
||||
goto LAB2; |
||||
|
||||
LAB3: goto *t2; |
||||
|
||||
LAB2: xsi_set_current_line(43, ng0); |
||||
t2 = (t0 + 3720); |
||||
xsi_process_wait(t2, 500000000LL); |
||||
*((char **)t1) = &&LAB4; |
||||
|
||||
LAB1: return; |
||||
LAB4: xsi_set_current_line(43, ng0); |
||||
t4 = (t0 + 2520); |
||||
t5 = (t4 + 56U); |
||||
t6 = *((char **)t5); |
||||
memset(t3, 0, 8); |
||||
t7 = (t6 + 4); |
||||
t8 = *((unsigned int *)t7); |
||||
t9 = (~(t8)); |
||||
t10 = *((unsigned int *)t6); |
||||
t11 = (t10 & t9); |
||||
t12 = (t11 & 1U); |
||||
if (t12 != 0) |
||||
goto LAB8; |
||||
|
||||
LAB6: if (*((unsigned int *)t7) == 0) |
||||
goto LAB5; |
||||
|
||||
LAB7: t13 = (t3 + 4); |
||||
*((unsigned int *)t3) = 1; |
||||
*((unsigned int *)t13) = 1; |
||||
|
||||
LAB8: t14 = (t3 + 4); |
||||
t15 = (t6 + 4); |
||||
t16 = *((unsigned int *)t6); |
||||
t17 = (~(t16)); |
||||
*((unsigned int *)t3) = t17; |
||||
*((unsigned int *)t14) = 0; |
||||
if (*((unsigned int *)t15) != 0) |
||||
goto LAB10; |
||||
|
||||
LAB9: t22 = *((unsigned int *)t3); |
||||
*((unsigned int *)t3) = (t22 & 1U); |
||||
t23 = *((unsigned int *)t14); |
||||
*((unsigned int *)t14) = (t23 & 1U); |
||||
t24 = (t0 + 2520); |
||||
xsi_vlogvar_assign_value(t24, t3, 0, 0, 1); |
||||
goto LAB2; |
||||
|
||||
LAB5: *((unsigned int *)t3) = 1; |
||||
goto LAB8; |
||||
|
||||
LAB10: t18 = *((unsigned int *)t3); |
||||
t19 = *((unsigned int *)t15); |
||||
*((unsigned int *)t3) = (t18 | t19); |
||||
t20 = *((unsigned int *)t14); |
||||
t21 = *((unsigned int *)t15); |
||||
*((unsigned int *)t14) = (t20 | t21); |
||||
goto LAB9; |
||||
|
||||
} |
||||
|
||||
static void Initial_47_1(char *t0) |
||||
{ |
||||
char *t1; |
||||
char *t2; |
||||
char *t3; |
||||
char *t4; |
||||
|
||||
LAB0: t1 = (t0 + 4160U); |
||||
t2 = *((char **)t1); |
||||
if (t2 == 0) |
||||
goto LAB2; |
||||
|
||||
LAB3: goto *t2; |
||||
|
||||
LAB2: xsi_set_current_line(47, ng0); |
||||
|
||||
LAB4: xsi_set_current_line(49, ng0); |
||||
t2 = ((char*)((ng1))); |
||||
t3 = (t0 + 2520); |
||||
xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); |
||||
xsi_set_current_line(50, ng0); |
||||
t2 = ((char*)((ng1))); |
||||
t3 = (t0 + 2680); |
||||
xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); |
||||
xsi_set_current_line(51, ng0); |
||||
t2 = ((char*)((ng1))); |
||||
t3 = (t0 + 2840); |
||||
xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); |
||||
xsi_set_current_line(52, ng0); |
||||
t2 = ((char*)((ng1))); |
||||
t3 = (t0 + 3000); |
||||
xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); |
||||
xsi_set_current_line(55, ng0); |
||||
t2 = ((char*)((ng2))); |
||||
t3 = (t0 + 2680); |
||||
xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); |
||||
xsi_set_current_line(56, ng0); |
||||
t2 = (t0 + 3968); |
||||
xsi_process_wait(t2, 500000000LL); |
||||
*((char **)t1) = &&LAB5; |
||||
|
||||
LAB1: return; |
||||
LAB5: xsi_set_current_line(56, ng0); |
||||
t3 = ((char*)((ng1))); |
||||
t4 = (t0 + 2680); |
||||
xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); |
||||
goto LAB1; |
||||
|
||||
} |
||||
|
||||
|
||||
extern void work_m_08900781484644397074_2259196339_init() |
||||
{ |
||||
static char *pe[] = {(void *)Always_42_0,(void *)Initial_47_1}; |
||||
xsi_register_didat("work_m_08900781484644397074_2259196339", "isim/verkeerslicht_tb_isim_beh.exe.sim/work/m_08900781484644397074_2259196339.didat"); |
||||
xsi_register_executes(pe); |
||||
} |
||||
Binary file not shown.
Binary file not shown.
@ -0,0 +1,337 @@ |
||||
/**********************************************************************/ |
||||
/* ____ ____ */ |
||||
/* / /\/ / */ |
||||
/* /___/ \ / */ |
||||
/* \ \ \/ */ |
||||
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ |
||||
/* / / All Right Reserved. */ |
||||
/* /---/ /\ */ |
||||
/* \ \ / \ */ |
||||
/* \___\/\___\ */ |
||||
/***********************************************************************/ |
||||
|
||||
/* This file is designed for use with ISim build 0xfbc00daa */ |
||||
|
||||
#define XSI_HIDE_SYMBOL_SPEC true |
||||
#include "xsi.h" |
||||
#include <memory.h> |
||||
#ifdef __GNUC__ |
||||
#include <stdlib.h> |
||||
#else |
||||
#include <malloc.h> |
||||
#define alloca _alloca |
||||
#endif |
||||
static const char *ng0 = "/opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/glbl.v"; |
||||
static unsigned int ng1[] = {1U, 0U}; |
||||
static unsigned int ng2[] = {0U, 0U}; |
||||
|
||||
|
||||
|
||||
static void NetDecl_16_0(char *t0) |
||||
{ |
||||
char *t1; |
||||
char *t2; |
||||
char *t3; |
||||
char *t4; |
||||
char *t5; |
||||
char *t6; |
||||
char *t7; |
||||
unsigned int t8; |
||||
unsigned int t9; |
||||
char *t10; |
||||
unsigned int t11; |
||||
unsigned int t12; |
||||
char *t13; |
||||
unsigned int t14; |
||||
unsigned int t15; |
||||
char *t16; |
||||
|
||||
LAB0: t1 = (t0 + 6952U); |
||||
t2 = *((char **)t1); |
||||
if (t2 == 0) |
||||
goto LAB2; |
||||
|
||||
LAB3: goto *t2; |
||||
|
||||
LAB2: xsi_set_current_line(16, ng0); |
||||
t2 = (t0 + 1960U); |
||||
t3 = *((char **)t2); |
||||
t2 = (t0 + 8640); |
||||
t4 = (t2 + 56U); |
||||
t5 = *((char **)t4); |
||||
t6 = (t5 + 56U); |
||||
t7 = *((char **)t6); |
||||
memset(t7, 0, 8); |
||||
t8 = 1U; |
||||
t9 = t8; |
||||
t10 = (t3 + 4); |
||||
t11 = *((unsigned int *)t3); |
||||
t8 = (t8 & t11) | ||||