]> Release 14.7 Trace (lin64)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved./opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml topFour.twx topFour.ncd -o topFour.twr topFour.pcf topFour.ncdtopFour.ncdtopFour.pcftopFour.pcfxc3s200-4PRODUCTION 1.39 2013-10-133INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.btn_0ld<0>9.105btn_0ld<1>10.220btn_0ld<2>9.992btn_0ld<3>12.303btn_0ld<4>12.137sw<0>ld<0>9.371sw<0>ld<1>10.486sw<0>ld<2>10.258sw<0>ld<3>12.569sw<0>ld<4>12.403sw<1>ld<1>9.144sw<1>ld<2>9.277sw<1>ld<3>11.588sw<1>ld<4>11.422sw<2>ld<2>8.226sw<2>ld<3>10.242sw<2>ld<4>10.076sw<3>ld<3>8.986sw<3>ld<4>9.795sw<4>ld<0>8.366sw<4>ld<1>9.481sw<4>ld<2>9.253sw<4>ld<3>11.564sw<4>ld<4>11.398sw<5>ld<1>8.781sw<5>ld<2>8.571sw<5>ld<3>10.882sw<5>ld<4>10.716sw<6>ld<2>7.573sw<6>ld<3>9.854sw<6>ld<4>9.688sw<7>ld<3>8.626sw<7>ld<4>8.974Mon Apr 4 15:13:27 2022 TraceTrace Settings Peak Memory Usage: 302 MB