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12 lines
1016 B
12 lines
1016 B
<?xml version="1.0" encoding="UTF-8"?> |
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<!-- IMPORTANT: This is an internal file that has been generated |
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by the Xilinx ISE software. Any direct editing or |
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changes made to this file may result in unpredictable |
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behavior or data corruption. It is strongly advised that |
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users do not edit the contents of this file. --> |
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<messages> |
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<msg type="info" file="Par" num="282" delta="new" >No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". |
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</msg> |
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</messages> |
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