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21 lines
1.7 KiB
21 lines
1.7 KiB
<?xml version="1.0" encoding="UTF-8"?> |
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<!-- IMPORTANT: This is an internal file that has been generated |
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by the Xilinx ISE software. Any direct editing or |
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changes made to this file may result in unpredictable |
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behavior or data corruption. It is strongly advised that |
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users do not edit the contents of this file. --> |
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<messages> |
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<msg type="info" file="Timing" num="2698" delta="new" >No timing constraints found, doing default enumeration.</msg> |
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<msg type="info" file="Timing" num="3412" delta="new" >To improve timing, see the Timing Closure User Guide (UG612).</msg> |
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<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg> |
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<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg> |
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<msg type="info" file="Timing" num="3390" delta="new" >This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</msg> |
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<msg type="info" file="Timing" num="3389" delta="new" >This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</msg> |
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</messages> |
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