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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : sch2hdl
-- / / Filename : fourBitAdder.vhf
-- /___/ /\ Timestamp : 04/04/2022 14:53:35
-- \ \ / \
-- \___\/\___\
--
--Command: sch2hdl -intstyle ise -family spartan3 -flat -suppress -vhdl "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.vhf" -w "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.sch"
--Design Name: fourBitAdder
--Device: spartan3
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesized and simulated, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity fourBitAdder is
port ( A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
Cin : in std_logic;
Cout : out std_logic;
Sum : out std_logic_vector (3 downto 0));
end fourBitAdder;
architecture BEHAVIORAL of fourBitAdder is
signal XLXN_26 : std_logic;
signal XLXN_27 : std_logic;
signal XLXN_28 : std_logic;
component oneBitAdder
port ( A : in std_logic;
B : in std_logic;
Cin : in std_logic;
Sum : out std_logic;
Cout : out std_logic);
end component;
begin
XLXI_1 : oneBitAdder
port map (A=>A(0),
B=>B(0),
Cin=>Cin,
Cout=>XLXN_26,
Sum=>Sum(0));
XLXI_2 : oneBitAdder
port map (A=>A(1),
B=>B(1),
Cin=>XLXN_26,
Cout=>XLXN_27,
Sum=>Sum(1));
XLXI_3 : oneBitAdder
port map (A=>A(2),
B=>B(2),
Cin=>XLXN_27,
Cout=>XLXN_28,
Sum=>Sum(2));
XLXI_4 : oneBitAdder
port map (A=>A(3),
B=>B(3),
Cin=>XLXN_28,
Cout=>Cout,
Sum=>Sum(3));
end BEHAVIORAL;