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57 lines
765 B
57 lines
765 B
// Verilog test fixture created from schematic /home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.sch - Mon Apr 4 14:43:23 2022 |
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`timescale 1ns / 1ps |
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module fourBitAdder_fourBitAdder_sch_tb(); |
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// Inputs |
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reg [3:0] A; |
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reg [3:0] B; |
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reg Cin; |
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// Output |
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wire Cout; |
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wire [3:0] Sum; |
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// Bidirs |
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// Instantiate the UUT |
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fourBitAdder UUT ( |
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.A(A), |
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.B(B), |
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.Cin(Cin), |
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.Cout(Cout), |
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.Sum(Sum) |
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); |
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initial begin |
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// All inputs 0, Cout and Sum should be 0 |
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A = 0; |
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B = 0; |
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Cin = 0; |
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#20; |
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// A and B bits 1 |
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A = 4'b1111; |
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B = 4'b1111; |
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Cin = 0; |
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#20; |
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A = 4'b1111; |
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B = 4'b1111; |
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Cin = 1; |
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#20; |
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A = 4'b0001; |
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B = 4'b1001; |
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Cin = 1; |
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// Expected: Sum = b1011; |
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end |
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endmodule
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