university-stuff/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitTest.v

// Verilog test fixture created from schematic /home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.sch - Mon Apr  4 14:43:23 2022

`timescale 1ns / 1ps

module fourBitAdder_fourBitAdder_sch_tb();

// Inputs
   reg [3:0] A;
   reg [3:0] B;
   reg Cin;

// Output
   wire Cout;
   wire [3:0] Sum;

// Bidirs

// Instantiate the UUT
   fourBitAdder UUT (
		.A(A), 
		.B(B), 
		.Cin(Cin), 
		.Cout(Cout), 
		.Sum(Sum)
   );

	initial begin

	
	// All inputs 0, Cout and Sum should be 0
	A = 0;
	B = 0;
	Cin = 0;
	
	#20;
	
	// A and B bits 1
	A = 4'b1111;
	B = 4'b1111;
	Cin = 0;
	
	#20;
	
	A = 4'b1111;
	B = 4'b1111;
	Cin = 1;
	
	#20;
	
	A = 4'b0001;
	B = 4'b1001;
	Cin = 1;
	// Expected: Sum = b1011;
	
	end
	
endmodule