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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:07:19 04/04/2022
// Design Name: oneBitAdder
// Module Name: /home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/oneBitTest.v
// Project Name: fourBitAdder
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: oneBitAdder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module oneBitTest;
// Inputs
reg A;
reg B;
reg Cin;
// Outputs
wire Sum;
wire Cout;
// Instantiate the Unit Under Test (UUT)
oneBitAdder uut (
.A(A),
.B(B),
.Cin(Cin),
.Sum(Sum),
.Cout(Cout)
);
integer i;
initial begin
// Initialize Inputs
A = 0;
B = 0;
Cin = 0;
// Wait 100 ns for global reset to finish
//#100;
// Add stimulus here
for (i = 1; i <= 8; i=i+1) begin
#20 A = ~A;
if (i % 2 == 0) B = ~B;
if (i % 4 == 0) Cin = ~Cin;
end
end
endmodule