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393 lines
16 KiB

Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.03 secs
-->
Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.03 secs
-->
Reading design: topFour.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "topFour.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "topFour"
Output Format : NGC
Target Device : xc3s200-4-ft256
---- Source Options
Top Module Name : topFour
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "HA.v" in library work
Compiling verilog file "oneBitAdder.v" in library work
Module <HA> compiled
Module <oneBitAdder> compiled
No errors in compilation
Analysis of file <"topFour.prj"> succeeded.
Compiling vhdl file "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/topFour.vhf" in Library work.
Entity <fourBitAdder_MUSER_topFour> compiled.
Entity <fourBitAdder_MUSER_topFour> (Architecture <BEHAVIORAL>) compiled.
Entity <IBUF8_MXILINX_topFour> compiled.
Entity <IBUF8_MXILINX_topFour> (Architecture <BEHAVIORAL>) compiled.
Entity <topFour> compiled.
Entity <topFour> (Architecture <BEHAVIORAL>) compiled.
Compiling vhdl file "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/fourBitAdder.vhf" in Library work.
Entity <fourBitAdder> compiled.
Entity <fourBitAdder> (Architecture <BEHAVIORAL>) compiled.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <topFour> in library <work> (architecture <BEHAVIORAL>).
Analyzing hierarchy for entity <IBUF8_MXILINX_topFour> in library <work> (architecture <BEHAVIORAL>).
Analyzing hierarchy for entity <fourBitAdder_MUSER_topFour> in library <work> (architecture <BEHAVIORAL>).
Analyzing hierarchy for module <oneBitAdder> in library <work>.
Analyzing hierarchy for module <HA> in library <work>.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <topFour> in library <work> (Architecture <BEHAVIORAL>).
Set user-defined property "LOC = m13" for signal <btn_0> in unit <topFour>.
Set user-defined property "LOC = k13 k14 j13 j14 h13 h14 g12 f12" for signal <sw> in unit <topFour>.
Set user-defined property "LOC = e13 f14 g14 d14" for signal <an> in unit <topFour>.
Set user-defined property "LOC = p11 p12 n12 p13 n14 l12 p14 k12" for signal <ld> in unit <topFour>.
Set user-defined property "LOC = e14" for signal <seg_a> in unit <topFour>.
Set user-defined property "LOC = g13" for signal <seg_b> in unit <topFour>.
Set user-defined property "LOC = n15" for signal <seg_c> in unit <topFour>.
Set user-defined property "LOC = p15" for signal <seg_d> in unit <topFour>.
Set user-defined property "LOC = p16" for signal <seg_dp> in unit <topFour>.
Set user-defined property "LOC = r16" for signal <seg_e> in unit <topFour>.
Set user-defined property "LOC = f13" for signal <seg_f> in unit <topFour>.
Set user-defined property "LOC = n16" for signal <seg_g> in unit <topFour>.
Set user-defined property "HU_SET = XLXI_17_0" for instance <XLXI_17> in unit <topFour>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <XLXI_20> in unit <topFour>.
Set user-defined property "DRIVE = 12" for instance <XLXI_34> in unit <topFour>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <XLXI_34> in unit <topFour>.
Set user-defined property "SLEW = SLOW" for instance <XLXI_34> in unit <topFour>.
Set user-defined property "DRIVE = 12" for instance <XLXI_35> in unit <topFour>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <XLXI_35> in unit <topFour>.
Set user-defined property "SLEW = SLOW" for instance <XLXI_35> in unit <topFour>.
Set user-defined property "DRIVE = 12" for instance <XLXI_36> in unit <topFour>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <XLXI_36> in unit <topFour>.
Set user-defined property "SLEW = SLOW" for instance <XLXI_36> in unit <topFour>.
Set user-defined property "DRIVE = 12" for instance <XLXI_37> in unit <topFour>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <XLXI_37> in unit <topFour>.
Set user-defined property "SLEW = SLOW" for instance <XLXI_37> in unit <topFour>.
Set user-defined property "DRIVE = 12" for instance <XLXI_38> in unit <topFour>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <XLXI_38> in unit <topFour>.
Set user-defined property "SLEW = SLOW" for instance <XLXI_38> in unit <topFour>.
Entity <topFour> analyzed. Unit <topFour> generated.
Analyzing Entity <IBUF8_MXILINX_topFour> in library <work> (Architecture <BEHAVIORAL>).
Set user-defined property "IOSTANDARD = DEFAULT" for instance <I_36_30> in unit <IBUF8_MXILINX_topFour>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <I_36_31> in unit <IBUF8_MXILINX_topFour>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <I_36_32> in unit <IBUF8_MXILINX_topFour>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <I_36_33> in unit <IBUF8_MXILINX_topFour>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <I_36_34> in unit <IBUF8_MXILINX_topFour>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <I_36_35> in unit <IBUF8_MXILINX_topFour>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <I_36_36> in unit <IBUF8_MXILINX_topFour>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <I_36_37> in unit <IBUF8_MXILINX_topFour>.
Entity <IBUF8_MXILINX_topFour> analyzed. Unit <IBUF8_MXILINX_topFour> generated.
Analyzing Entity <fourBitAdder_MUSER_topFour> in library <work> (Architecture <BEHAVIORAL>).
Entity <fourBitAdder_MUSER_topFour> analyzed. Unit <fourBitAdder_MUSER_topFour> generated.
Analyzing module <oneBitAdder> in library <work>.
Module <oneBitAdder> is correct for synthesis.
Analyzing module <HA> in library <work>.
Module <HA> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <HA>.
Related source file is "HA.v".
Found 1-bit xor2 for signal <s>.
Unit <HA> synthesized.
Synthesizing Unit <IBUF8_MXILINX_topFour>.
Related source file is "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/topFour.vhf".
Unit <IBUF8_MXILINX_topFour> synthesized.
Synthesizing Unit <oneBitAdder>.
Related source file is "oneBitAdder.v".
Unit <oneBitAdder> synthesized.
Synthesizing Unit <fourBitAdder_MUSER_topFour>.
Related source file is "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/topFour.vhf".
Unit <fourBitAdder_MUSER_topFour> synthesized.
Synthesizing Unit <topFour>.
Related source file is "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/topFour.vhf".
Unit <topFour> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Xors : 8
1-bit xor2 : 8
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Xors : 8
1-bit xor2 : 8
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <topFour> ...
Optimizing unit <IBUF8_MXILINX_topFour> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topFour, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : topFour.ngr
Top Level Output File Name : topFour
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 29
Cell Usage :
# BELS : 10
# GND : 1
# LUT3 : 8
# VCC : 1
# IO Buffers : 29
# IBUF : 9
# OBUF : 20
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s200ft256-4
Number of Slices: 4 out of 1920 0%
Number of 4 input LUTs: 8 out of 3840 0%
Number of IOs: 29
Number of bonded IOBs: 29 out of 173 16%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 13.902ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 33 / 5
-------------------------------------------------------------------------
Delay: 13.902ns (Levels of Logic = 7)
Source: sw<4> (PAD)
Destination: ld<4> (PAD)
Data Path: sw<4> to ld<4>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
begin scope: 'XLXI_17'
IBUF:I->O 2 0.821 1.216 I_36_30 (O<4>)
end scope: 'XLXI_17'
LUT3:I0->O 2 0.551 1.072 XLXI_58/XLXI_1/Cout1 (XLXI_58/XLXN_26)
LUT3:I1->O 2 0.551 1.072 XLXI_58/XLXI_2/Cout1 (XLXI_58/XLXN_27)
LUT3:I1->O 2 0.551 1.072 XLXI_58/XLXI_3/Cout1 (XLXI_58/XLXN_28)
LUT3:I1->O 1 0.551 0.801 XLXI_58/XLXI_4/Cout1 (cout)
OBUF:I->O 5.644 XLXI_38 (ld<4>)
----------------------------------------
Total 13.902ns (8.669ns logic, 5.233ns route)
(62.4% logic, 37.6% route)
=========================================================================
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 2.13 secs
-->
Total memory usage is 512360 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)