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-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : sch2hdl
-- / / Filename : topFour.vhf
-- /___/ /\ Timestamp : 04/04/2022 15:13:15
-- \ \ / \
-- \___\/\___\
--
--Command: sch2hdl -intstyle ise -family spartan3 -flat -suppress -vhdl "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/topFour.vhf" -w "/home/daan/Documents/School/Digitale elektronica en processoren/practicum/fourBitAdder/topFour.sch"
--Design Name: topFour
--Device: spartan3
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesized and simulated, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity fourBitAdder_MUSER_topFour is
port ( A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
Cin : in std_logic;
Cout : out std_logic;
Sum : out std_logic_vector (3 downto 0));
end fourBitAdder_MUSER_topFour;
architecture BEHAVIORAL of fourBitAdder_MUSER_topFour is
signal XLXN_26 : std_logic;
signal XLXN_27 : std_logic;
signal XLXN_28 : std_logic;
component oneBitAdder
port ( A : in std_logic;
B : in std_logic;
Cin : in std_logic;
Sum : out std_logic;
Cout : out std_logic);
end component;
begin
XLXI_1 : oneBitAdder
port map (A=>A(0),
B=>B(0),
Cin=>Cin,
Cout=>XLXN_26,
Sum=>Sum(0));
XLXI_2 : oneBitAdder
port map (A=>A(1),
B=>B(1),
Cin=>XLXN_26,
Cout=>XLXN_27,
Sum=>Sum(1));
XLXI_3 : oneBitAdder
port map (A=>A(2),
B=>B(2),
Cin=>XLXN_27,
Cout=>XLXN_28,
Sum=>Sum(2));
XLXI_4 : oneBitAdder
port map (A=>A(3),
B=>B(3),
Cin=>XLXN_28,
Cout=>Cout,
Sum=>Sum(3));
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity IBUF8_MXILINX_topFour is
port ( I : in std_logic_vector (7 downto 0);
O : out std_logic_vector (7 downto 0));
end IBUF8_MXILINX_topFour;
architecture BEHAVIORAL of IBUF8_MXILINX_topFour is
attribute IOSTANDARD : string ;
attribute BOX_TYPE : string ;
component IBUF
port ( I : in std_logic;
O : out std_logic);
end component;
attribute IOSTANDARD of IBUF : component is "DEFAULT";
attribute BOX_TYPE of IBUF : component is "BLACK_BOX";
begin
I_36_30 : IBUF
port map (I=>I(4),
O=>O(4));
I_36_31 : IBUF
port map (I=>I(5),
O=>O(5));
I_36_32 : IBUF
port map (I=>I(6),
O=>O(6));
I_36_33 : IBUF
port map (I=>I(7),
O=>O(7));
I_36_34 : IBUF
port map (I=>I(3),
O=>O(3));
I_36_35 : IBUF
port map (I=>I(2),
O=>O(2));
I_36_36 : IBUF
port map (I=>I(1),
O=>O(1));
I_36_37 : IBUF
port map (I=>I(0),
O=>O(0));
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity topFour is
port ( btn_0 : in std_logic;
sw : in std_logic_vector (7 downto 0);
an : out std_logic_vector (3 downto 0);
ld : out std_logic_vector (7 downto 0);
seg_a : out std_logic;
seg_b : out std_logic;
seg_c : out std_logic;
seg_d : out std_logic;
seg_dp : out std_logic;
seg_e : out std_logic;
seg_f : out std_logic;
seg_g : out std_logic);
attribute LOC : string ;
attribute LOC of btn_0 : signal is "m13";
attribute LOC of sw : signal is "k13,k14,j13,j14,h13,h14,g12,f12";
attribute LOC of an : signal is "e13,f14,g14,d14";
attribute LOC of ld : signal is "p11,p12,n12,p13,n14,l12,p14,k12";
attribute LOC of seg_a : signal is "e14";
attribute LOC of seg_b : signal is "g13";
attribute LOC of seg_c : signal is "n15";
attribute LOC of seg_d : signal is "p15";
attribute LOC of seg_dp : signal is "p16";
attribute LOC of seg_e : signal is "r16";
attribute LOC of seg_f : signal is "f13";
attribute LOC of seg_g : signal is "n16";
end topFour;
architecture BEHAVIORAL of topFour is
attribute BOX_TYPE : string ;
attribute HU_SET : string ;
attribute IOSTANDARD : string ;
attribute SLEW : string ;
attribute DRIVE : string ;
signal cout : std_logic;
signal sum : std_logic_vector (3 downto 0);
signal switch : std_logic_vector (7 downto 0);
signal XLXN_6 : std_logic;
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component IBUF8_MXILINX_topFour
port ( I : in std_logic_vector (7 downto 0);
O : out std_logic_vector (7 downto 0));
end component;
component IBUF
port ( I : in std_logic;
O : out std_logic);
end component;
attribute IOSTANDARD of IBUF : component is "DEFAULT";
attribute BOX_TYPE of IBUF : component is "BLACK_BOX";
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component OBUF
port ( I : in std_logic;
O : out std_logic);
end component;
attribute IOSTANDARD of OBUF : component is "DEFAULT";
attribute SLEW of OBUF : component is "SLOW";
attribute DRIVE of OBUF : component is "12";
attribute BOX_TYPE of OBUF : component is "BLACK_BOX";
component fourBitAdder_MUSER_topFour
port ( A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
Cin : in std_logic;
Cout : out std_logic;
Sum : out std_logic_vector (3 downto 0));
end component;
attribute HU_SET of XLXI_17 : label is "XLXI_17_0";
begin
XLXI_2 : GND
port map (G=>ld(6));
XLXI_3 : GND
port map (G=>ld(5));
XLXI_4 : GND
port map (G=>ld(7));
XLXI_17 : IBUF8_MXILINX_topFour
port map (I(7 downto 0)=>sw(7 downto 0),
O(7 downto 0)=>switch(7 downto 0));
XLXI_20 : IBUF
port map (I=>btn_0,
O=>XLXN_6);
XLXI_21 : VCC
port map (P=>an(0));
XLXI_22 : VCC
port map (P=>an(1));
XLXI_23 : VCC
port map (P=>an(2));
XLXI_25 : VCC
port map (P=>seg_a);
XLXI_26 : VCC
port map (P=>seg_b);
XLXI_27 : VCC
port map (P=>seg_c);
XLXI_28 : VCC
port map (P=>seg_d);
XLXI_29 : VCC
port map (P=>seg_e);
XLXI_30 : VCC
port map (P=>seg_f);
XLXI_31 : VCC
port map (P=>seg_g);
XLXI_32 : GND
port map (G=>seg_dp);
XLXI_34 : OBUF
port map (I=>sum(0),
O=>ld(0));
XLXI_35 : OBUF
port map (I=>sum(1),
O=>ld(1));
XLXI_36 : OBUF
port map (I=>sum(2),
O=>ld(2));
XLXI_37 : OBUF
port map (I=>sum(3),
O=>ld(3));
XLXI_38 : OBUF
port map (I=>cout,
O=>ld(4));
XLXI_57 : GND
port map (G=>an(3));
XLXI_58 : fourBitAdder_MUSER_topFour
port map (A(3 downto 0)=>switch(3 downto 0),
B(3 downto 0)=>switch(7 downto 4),
Cin=>XLXN_6,
Cout=>cout,
Sum(3 downto 0)=>sum(3 downto 0));
end BEHAVIORAL;