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Release 14.7 Map P.20131013 (lin64)
Xilinx Map Application Log File for Design 'topFour'
Design Information
Command Line : map -intstyle ise -p xc3s200-ft256-4 -cm area -ir off -pr off
-c 100 -o topFour_map.ncd topFour.ngd topFour.pcf
Target Device : xc3s200
Target Package : ft256
Target Speed : -4
Mapper Version : spartan3 -- $Revision: 1.55 $
Mapped Date : Mon Apr 4 15:13:23 2022
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...
Design Summary
Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of 4 input LUTs: 8 out of 3,840 1%
Logic Distribution:
Number of occupied Slices: 6 out of 1,920 1%
Number of Slices containing only related logic: 6 out of 6 100%
Number of Slices containing unrelated logic: 0 out of 6 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 8 out of 3,840 1%
Number of bonded IOBs: 29 out of 173 16%
Average Fanout of Non-Clock Nets: 1.71
Peak Memory Usage: 513 MB
Total REAL time to MAP completion: 0 secs
Total CPU time to MAP completion: 0 secs
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Mapping completed.
See MAP report file "topFour_map.mrp" for details.